If debug is implemented, the processor provides debug through
registers in the SCS, see Debug register summary.
SCS CoreSight identification
Table 6.3 shows
the SCS CoreSight identification registers and values for debugger detection. Final
debugger identification of the Cortex-M0 processor is through the CPUID
register in the SCS, see CPUID Register.
Table 6.3. SCS identification values
| Register | Value | Description |
|---|
| Peripheral ID4 | 0x00000004 | Component and Peripheral
ID register formats in the ARMv6-M ARM |
| Peripheral ID0 | 0x00000008 |
| Peripheral ID1 | 0x000000B0 |
| Peripheral ID2 | 0x0000000B |
| Peripheral ID3 | 0x00000000 |
| Component ID0 | 0x0000000D |
| Component ID1 | 0x000000E0 |
| Component ID2 | 0x00000005 |
| Component ID3 | 0x000000B1 |
See the ARMv6-M ARM and the ARM
CoreSight Components Technical Reference Manual for
more information about the SCS CoreSight identification registers,
and their addresses and access types.
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