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Table 3.3 shows the processor core register set summary. Each of these registers is 32 bits wide.
Table 3.3. Processor core register set summary
| Name | Description |
|---|---|
| R0-R12 | R0-R12 are general-purpose registers for data operations. |
| MSP (R13) | The Stack Pointer (SP) is register R13. In Thread mode, the CONTROLregister indicates the stack pointer to use, Main Stack Pointer (MSP) or Process Stack Pointer (PSP). |
| PSP (R13) | |
| LR (R14) | The Link Register (LR) is register R14. It stores the return information for subroutines,function calls, and exceptions. |
| PC (R15) | The Program Counter (PC) is register R15. It contains the current program address. |
| PSR | The Program Status Register (PSR) combines:
These registers provide different views of the PSR. |
| PRIMASK | The PRIMASK register prevents activation of all exceptions with configurable priority. For information about the exception model the processor supports, see Exceptions. |
| CONTROL | The CONTROL register controls the stack used when the processor is in Thread mode. |
See the ARMv6-M ARM for information about the processor core registers and their addresses, access types, and reset values.
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0432C |
| Non-Confidential | |
| PDF version | |
| Home > Programmers Model > Processor core registers summary |