10.2.7. Common Event Identification Registers

The PMCEID0 and PMCEID1 Register characteristics are:


Define which common architectural and common micro-architectural feature events are implemented.

Usage constraints

The PMCEID0 and PMCEID1 Registers are:


Available in all configurations.


See the register summary in Table 4.17.

Table 10.8 shows the PMCEID0 Register bit assignments and which features are implemented in the Cortex-A5 processor.

Table 10.8. PMCEID0 Register bit assignments

BitNumber DescriptionImplemented?
[31:30]0x1F-0x1EReserved, UNK.-
[29]0x1D Bus cycleNo
[28] 0x1C Write to translation table baseNo
[27] 0x1B Instruction speculatively executedNo
[26] 0x1ALocal memory errorNo
[25] 0x19 Bus accessNo
[24] 0x18Level 2 data cache write-backNo
[23]0x17Level 2 data cache refillNo
[22]0x16Level 2 data cache accessNo
[21] 0x15Level 1 data cache write-backYes
[20] 0x14 Level 1 instruction cache accessYes
[19] 0x13 Data memory accessYes
[18] 0x12 Predictable branch speculatively executedYes
[17] 0x11 CycleYes
[16] 0x10 Mispredicted or not predicted branch speculatively executedYes
[15] 0x0F Unaligned load or storeYes
[14] 0x0EProcedure returnYes
[13] 0x0D Immediate branchYes
[12] 0x0C Software change of the PCYes
[11] 0x0B Write to CONTEXTIDRYes
[10] 0x0AException returnYes
[9] 0x09Exception takenYes
[8] 0x08Instruction architecturally executedYes
[7] 0x07StoreYes
[6] 0x06 LoadYes
[5] 0x05 Level 1 data TLB refillYes
[4] 0x04 Level 1 data cache accessYes
[3] 0x03 Level 1 data cache refillYes
[2] 0x02 Level 1 instruction TLB refillYes
[1] 0x01 Level 1 instruction cache refillYes
[0] 0x00 Software incrementYes

The PMCEID1 Register is reserved in the architecture, and is RAZ/WI.

To access the PMCEID0 Register, use:

MRC p15, 0, <Rd>, c9, c12, 6; Read PMCEID0

To access the PMCEID1 Register, use:

MRC p15, 0, <Rd>, c9, c12, 7; Read PMCEID1
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