Cortex-A5 Technical Reference Manual: 10.2.7. Common Event Identification Registers

The PMCEID0 and PMCEID1 Register characteristics are:

Purpose

Define which common architectural and common micro-architectural feature events are implemented.

Usage constraints

The PMCEID0 and PMCEID1 Registers are:

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.17.

Table 10.8 shows the PMCEID0 Register bit assignments and which features are implemented in the Cortex-A5 processor.

Table 10.8. PMCEID0 Register bit assignments

Bit	Number	Description	Implemented?
[31:30]	`0x1F`-`0x1E`	Reserved, UNK.	-
[29]	`0x1D`	Bus cycle	No
[28]	`0x1C`	Write to translation table base	No
[27]	`0x1B`	Instruction speculatively executed	No
[26]	`0x1A`	Local memory error	No
[25]	`0x19`	Bus access	No
[24]	`0x18`	Level 2 data cache write-back	No
[23]	`0x17`	Level 2 data cache refill	No
[22]	`0x16`	Level 2 data cache access	No
[21]	`0x15`	Level 1 data cache write-back	Yes
[20]	`0x14`	Level 1 instruction cache access	Yes
[19]	`0x13`	Data memory access	Yes
[18]	`0x12`	Predictable branch speculatively executed	Yes
[17]	`0x11`	Cycle	Yes
[16]	`0x10`	Mispredicted or not predicted branch speculatively executed	Yes
[15]	`0x0F`	Unaligned load or store	Yes
[14]	`0x0E`	Procedure return	Yes
[13]	`0x0D`	Immediate branch	Yes
[12]	`0x0C`	Software change of the PC	Yes
[11]	`0x0B`	Write to CONTEXTIDR	Yes
[10]	`0x0A`	Exception return	Yes
[9]	`0x09`	Exception taken	Yes
[8]	`0x08`	Instruction architecturally executed	Yes
[7]	`0x07`	Store	Yes
[6]	`0x06`	Load	Yes
[5]	`0x05`	Level 1 data TLB refill	Yes
[4]	`0x04`	Level 1 data cache access	Yes
[3]	`0x03`	Level 1 data cache refill	Yes
[2]	`0x02`	Level 1 instruction TLB refill	Yes
[1]	`0x01`	Level 1 instruction cache refill	Yes
[0]	`0x00`	Software increment	Yes

The PMCEID1 Register is reserved in the architecture, and is RAZ/WI.

To access the PMCEID0 Register, use:

MRC p15, 0, <Rd>, c9, c12, 6; Read PMCEID0

To access the PMCEID1 Register, use:

MRC p15, 0, <Rd>, c9, c12, 7; Read PMCEID1

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