The system can access memory-mapped debug registers through the Cortex-A5 APB slave port.

The APB interface is compliant with the AMBA 3 APB interface. This APB slave interface supports 32-bits wide data, stalls, slave-generated aborts, and eleven address bits [12:2] mapping 2x4KB of memory. The lower 4KB region is used to access the debug registers. The upper 4KB is used to access the Performance Monitor Registers, see Chapter 10 Performance Monitoring Unit. The PADDRDBG31 signal indicates to the processor the source of access. See External debug interface for a complete list of the external debug signals.

Figure 9.19 shows the external debug interface signals.