| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
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Table 1.1 shows the Cortex-A5 processor RTL configurable options.
Table 1.1. Configurable options for the Cortex-A5 processor
| Feature | Range of options | Default value |
|---|---|---|
| Instruction cache size | 4KB, 8KB, 16KB, 32KB, or 64KB | Implementation dependent |
| Data cache size | 4KB, 8KB, 16KB, 32KB, or 64KB | Implementation dependent |
| Floating Point Unit or Media Processing Engine (NEON) | None, VFPv4-D16, or VFPv4 and NEON | Not included |
| Jazelle Architecture Extension | Full or trivial | Trivial |
| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > Introduction > Configurable options |