Cortex-A5 Technical Reference Manual: 9.6. Management registers

9.6. Management registers

The management registers define the standardized set of registers implemented by all CoreSight components. These registers are described in this section.

Table 9.15 shows the contents of the management registers for the Cortex-A5 processor debug unit.

Table 9.15. Management registers

Offset	Register number	Access	Mnemonic	Description
`0xD00-0xDFC`	832-895	RO	-	Processor ID Registers
`0xE00-0xEF0`	854-957	-	-	RAZ
`0xF00`	960	RW	DBGITCTRL	Integration Mode Control Register.
`0xF04-0xF9C`	961-999	RAZ	-	Reserved for Management Register expansion
`0xFA0`	1000	RW	DBGCLAIMSET	Claim Tag Set Register
`0xFA4`	1001	RW	DBGCLAIMCLR	Claim Tag Clear Register
`0xFA8-0xFBC`	1002-1003	-	-	RAZ
`0xFB0`	1004	WO	DBGLAR	Lock Access Register
`0xFB4`	1005	RO	DBGLSR	Lock Status Register
`0xFB8`	1006	RO	DBGAUTHSTATUS	Authentication Status Register
`0xFBC-0xFC4`	1007-1009	-	-	RAZ
`0xFC8`	1010	RO	DBGDEVID	Device Identifier.
`0xFCC`	1011	RO	DBGDEVTYPE	Device Type Register
`0xFD0-0xFFC`	1012-1023	RO	-	Identification Registers

Copyright © 2009, 2010 ARM. All rights reserved.	ARM DDI 0433B
Non-Confidential	ID101810
PDF version