Cortex-A5 Technical Reference Manual: 9.4. Debug register summary

9.4. Debug register summary

You can access the debug registers:

through the CP14 interface. The debug registers are mapped to coprocessor instructions.
through a 4KB memory-mapped region on the APB interface when PADDRDBG[12] is b0 and using the relevant offset, with the following exceptions:
- DBGRAR
- DBGSAR
- DBGDSCRint
- DBGDTRTXint
- DBGDTRRXint.

External views of DBGDSCR , DBGDTRRX, and DBGDTRTX are accessible through memory-mapped APB access.

Table 9.1 shows the debug interface registers, including the CP14 instruction encoding and the address offset in the 4KB memory mapped region on the APB interface.

Table 9.1. Debug interface registers

Register number	Offset	CP14 instruction	Access	Name	Description
0	`0x000`	`0 c0 c0 0`	RO	DBGDIDR^[a]	Debug Identification Register ^[b]
128	-	`0 c1 c0 0`	RO	DBGDRAR^a	-
256	-	`0 c2 c0 0`	RO	DBGDSAR^a	-
1	-	`0 c0 c1 0`	RO	DBGDSCR-int^a^b	Debug Status and Control Register ^[a]
2-4	-	-	-	Reserved	-
5	-	`0 c0 c5 0`	RW	DBGDTRTXint (writes) and DBGDTRRXint (reads)^a	-
6	`0x018`	`0 c0 c6 0`	RW	DBGWFAR	Use of DBGWFAR is deprecated in the ARMv7 architecture, because watchpoints are synchronous
7	`0x01C`	`0 c0 c7 0`	RW	DBGVCR	-
8	-	-	-	Reserved	-
9	`0x024`	`0 c0 c9 0`	RAZ/WI	DBGECR	Event Catch Register
10	`0x028`	`0 c0 c10 0`	RAZ/WI	DBGDSCCR	Debug State Cache Control Register
11	`0x02C`	`0 c0 c11 0`	RAZ/WI	DBGDSMCR	Debug State MMU Control Register
12-31	-	-	-	Reserved	-
32	`0x080`	`0 c0 c0 2`	RW	DBGDTRRXext	-
33	`0x084`	-	WO	DBGITR	-
33	`0x084`	-	RO	DBGPCSR	Program Counter Sampling Register
34	`0x088`	`0 c0 c2 2`	RW	DBGDSCRext	Debug Status and Control Register
35	`0x08C`	`0 c0 c3 2`	RW	DBGDTRTXext	-
36	`0x090`	`0 c0 c4 2`	WO	DBGDRCR	Debug Run Control Register
37-39	-	-	-	Reserved	-
40	`0x0A0`	-	RO	DBGPCSR	Program Counter Sampling Register
41	`0x0A4`	-	RO	DBGCIDSR	-
42-63	-	-	-	Reserved	-
64-79	`0x100`-`0x13C`	`0 c0 c0-2 4`	RW	DBGBVRn	Breakpoint Value Registers
80-95	`0x140`-`0x17C`	`0 c0 c0-2 5`	RW	DBGBCRn	Breakpoint Control Registers
96-111	`0x180`-`0x1BC`	`0 c0 c0-1 6`	RW	DBGWVRn	Watchpoint Value Register
129-255, 257-191	`0x1C0`-`0x1FC`	`0 c0 c0-1 7`	RW	DBGWCRn	Watchpoint Control Register
128-191	-	-	-	Reserved	-
192	`0x300`	`0 c1 c0 4`	WO/WI	DBGOSLAR	Operating System Lock and Save/Restore Registers
193	`0x304`	`0 c1 c1 4`	RO/RAZ	DBGOSLSR
194	`0x308`	`0 c1 c2 4`	RAZ/WI	DBGOSSRR
195	-	-	-	Reserved	-
196	`0x310`	`0 c1 c4 4`	RW	DBGPRCR	Device Power-down and Reset Control Register
197	`0x314`	`0 c1 c5 4`	RO	DBGPRSR	Device Power-down and Reset Status Register
198-831	-	-	-	Reserved	-
832-895	`0xD00`-`0xDFC`	-^[c]	RO	-	Processor ID Registers
896-957	-	-	-	Reserved	-
958	`0xEF8`	-	WO	DBGITMISCOUT	DBGITMISCOUT Register (Miscellaneous Outputs)
959	`0xEFC`	-	RO	DBGITMISCIN	DBGITMISCIN Register (Miscellaneous Inputs)
960	`0xF00`	-	RAZ/WI	DBGITCTRL	Integration Mode Control Register
961-999	`0xF04`-`0xF9C`	-	-	Reserved	-
1000	`0xFA0`	`0 c7 c8 6`	RW	DBGCLAIMSET	Claim Tag Set Register
1001	`0xFA4`	`0 c7 c9 6`	RW	DBGCLAIMCLR	Claim Tag Clear Register
1002-1003	-	-	-	Reserved	-
1004	`0xFB0`	-	WO	DBGLAR	Lock Access Register
1005	`0xFB4`	-	RO	DBGLSR	Lock Status Register
1006	`0xFB8`	`0 c7 c14 6`	RO	DBGAUTHSTATUS	Authentication Status Register
1007-1009	-	-	-	Reserved	-
1010	`0xFC8`	`0 c7 c2 7`	RO	DBGDEVID	-
1011	`0xFCC`	-	RO	DBGDEVTYPE	Device Type Register
1012-1016	`0xFD0`-`0xFEC`	-	RO	PERIPHERALID	Identification Registers
1017-1019	-	-	-	Reserved	-
1020-1023	`0xFF0`-`0xFFC`	-	RO	COMPONENTID	Identification Registers
^[a]Baseline CP14 interface. This register also has an external view through the memory-mapped interface and the CP14 interface. See Debug Status and Control Register. ^[b]Accessible in User mode if bit [12] of the DBGDSCR is clear. Also accessible in privileged modes. ^[c]Accessed through CP15 interface.

Copyright © 2009, 2010 ARM. All rights reserved.	ARM DDI 0433B
Non-Confidential	ID101810
PDF version