Cortex-A5 Technical Reference Manual: 10.2.20. Identification Registers

10.2.20. Identification Registers

The Identification Registers are read-only registers that consist of the Peripheral Identification Registers and the Component Identification Registers. The Peripheral Identification Registers provide standard information required by all CoreSight components. Only bits [7:0] of each register are used.

The Component Identification Registers identify the processor as a CoreSight component. Only bits [7:0] of each register are used, the remaining bits Read-As-Zero. The values in these registers are fixed.

Table 10.21 shows the offset value, register number, and description that are associated with each Peripheral Identification Register.

Table 10.21. Peripheral Identification Registers

Offset (hex)	Register number	Description
`0x1FD0`	1012	Peripheral Identification Register 4
`0x1FD4`	1013	Reserved
`0x1FD8`	1014	Reserved
`0x1FDC`	1015	Reserved
`0x1FE0`	1016	Peripheral Identification Register 0
`0x1FE4`	1017	Peripheral Identification Register 1
`0x1FE8`	1018	Peripheral Identification Register 2
`0x1FEC`	1019	Peripheral Identification Register 3

Table 10.22 shows the Peripheral ID Register 0 bit assignments.

Table 10.22. Peripheral ID Register 0 bit assignments

Bits	Description
[31:8]	RAZ.
[7:0]	Indicates bits [7:0] of the part number for the Cortex-A5 processor. This value is `0xA5`.

Table 10.23 shows the Peripheral ID Register 1 bit assignments.

Table 10.23. Peripheral ID Register 1 bit assignments

Bits	Description
[31:8]	RAZ.
[7:4]	Indicates bits of the JEDEC JEP106 Identity Code. This value is `0xB`.
[3:0]	Indicates bits [11:8] of the part number for the Cortex-A5 processor. This value is `0x9`.

Table 10.24 shows the Peripheral ID Register 2 bit assignments.

Table 10.24. Peripheral ID Register 2 bit assignments

Bits	Description
[31:8]	RAZ.
[7:4]	Indicates the revision number for the Cortex-A5 processor. This value changes based on the product major and minor revision. This value is set to 1 indicating revision r0p1.
[3]	This field is always set to `0x1`.
[2:0]	Indicates bits [6:4] of the JEDEC JEP106 Identity Code. This value is set to `0x3`.

Table 10.25 shows the Peripheral ID Register 3 bit assignments.

Table 10.25. Peripheral ID Register 3 bit assignments

Bits	Description
[31:8]	RAZ.
[7:4]	Indicates the manufacturer revision number. This value changes based on the manufacturer metal fixes. This value is set to 0.
[3:0]	For the Cortex-A5 processor, this value is set to 0.

Table 10.26 shows the Peripheral ID Register 4 bit assignments.

Table 10.26. Peripheral ID Register 4 bit assignments

Bits	Description
[31:8]	RAZ.
[7:4]	Indicates the number of blocks occupied by the Cortex-A5 processor. This field is always set to 0.
[3:0]	Indicates the JEDEC JEP106 Continuation Code. For the Cortex-A5 processor, this value is `0x4`.

Table 10.27 shows the offset value, register number, and value that are associated with each Component Identification Register.

Table 10.27. Component Identification Registers

Offset (hex)	Register number	Value	Description
`0x1FF0`	1020	`0x0D`	Component Identification Register 0
`0x1FF4`	1021	`0x90`	Component Identification Register 1
`0x1FF8`	1022	`0x05`	Component Identification Register 2
`0x1FFC`	1023	`0xB1`	Component Identification Register 3

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