[31]

RAZ on reads, SBZP on writes.

[30]

RXfull

The DBGDTRRX Register full flag:

0 = DBGDTRRX empty, reset value

1 = DBGDTRRX full.

When set, this flag indicates that there is data available in the Receive Data Transfer Register, DBGDTRRX. It is automatically set on writes to the DBGDTRRXext by the debugger, and is cleared when the processor reads the CP14 DBGDTRRXint. If the flag is not set, reads of the DBGDTRRX return an Unpredictable value.

[29]

TXfull

The DBGDTRTX Register full flag:

0 = DBGDTRTX empty, reset value

1 = DBGDTRTX full.

When clear, this flag indicates that the Transmit Data Transfer Register, DBGDTRTX is ready for data write. It is automatically cleared on reads of the DBGDTRTXext by the debugger, and is set when the processor writes to the CP14 DBGDTRTXint. If this bit is set and the processor attempts to write to the DBGDTRTXint, results are Unpredictable.

[28]

RAZ on reads, SBZP on writes.

[27]

The latched DBGDTRRX Register full flag. This flag is read in one of the following ways:

Reads of DBGDSCRint return an Unpredictable value for this bit.

Reads of DBGDSCRext return the same value as RXfull.

If a write to the DBGDTRRXext address succeeds, RXfull_l is set to 1.

[26]

The latched DBGDTRTX Register full flag. This flag is read in one of the following ways:

Reads of DBGDSCRint return an Unpredictable value for this bit.

Reads of DBGDSCRext return the same value as TXfull.

If a read to the DBGDTRTXext address succeeds, TXfull_l is cleared.

[25]

Sticky pipeline advance bit. This bit enables the debugger to detect whether the processor is idle. In some situations, this might mean that the system bus port is deadlocked. This bit is set to 1 every time the processor pipeline retires one instruction. A write to DBGDRCR[3] clears this bit. See Debug Run Control Register.

0 = no instruction has completed execution since the last time this bit was cleared, reset value

1 = an instruction has completed execution since the last time this bit was cleared.

[24]

InstrCompl_l

The latched InstrCompl flag. This flag is read in one of the following ways:

When in Non-debug state, all reads of DBGDSCR return an Unpredictable value for this bit. Otherwise, reads through the CP14 interface return an Unpredictable value for this bit.

Reads of the DBGDSCRext APB address return the same value as InstrCompl.

If a write to the DBGITR APB address succeeds while in Stall or Nonblocking mode, InstrCompl_l and InstrCompl are cleared.

If a write to the DBGDTRRXext APB address or a read to the DBGDTRTXext APB address succeeds while in Fast mode, InstrCompl_l and InstrCompl are cleared.

InstrCompl is the instruction complete bit. This internal flag determines whether the processor has completed execution of an instruction issued through the APB interface.

0 = the processor is currently executing an instruction fetched from the DBGITR Register, reset value

1 = the processor is not currently executing an instruction fetched from the DBGITR Register.

[23:22]

RAZ on reads, SBZP on writes.

[21:20]

External DCC access mode. This is a read and write field. You can use this field to optimize DTR and DBGITR traffic between a debugger and the processor:

b00 = Nonblocking mode, reset value

b01 = Stall mode

b10 = Fast mode

b11 = reserved.

See External DCC and DBGITR access mode for more information.

[19]

Discard asynchronous abort. This read-only bit is set while the processor is in debug state and is cleared on exit from debug state. While this bit is set, the processor does not record asynchronous Data Aborts. However, the sticky asynchronous Data Abort bit is set to 1.

0 = asynchronous Data Aborts not discarded, reset value

1 = asynchronous Data Aborts discarded.

[18]^[a]

Non-secure state status bit:

0 = the processor is in Secure state or the processor is in Monitor mode

1 = the processor is in Non-secure state and is not in Monitor mode.

[17]^a

Secure privileged noninvasive debug disabled:

0 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is HIGH

1 = ((NIDEN || DBGEN) && (SPNIDEN || SPIDEN)) is LOW.

This value is the inverse of bit [6] of the Authentication Status Register. See Authentication Status Register.

[16]^a

Secure privileged invasive debug disabled:

0 = (DBGEN && SPIDEN) is HIGH

1 = (DBGEN && SPIDEN) is LOW.

This value is the inverse of bit [4] of the Authentication Status Register. See Authentication Status Register.

[15]

The Monitor debug-mode enable bit. This is a read and write bit.

0 = Monitor debug-mode disabled, reset value

1 = Monitor debug-mode enabled.

If Halting debug-mode is enabled, bit [14] is set, then the processor is in Halting debug-mode regardless of the value of bit [15]. If the external interface input DBGEN is LOW, DBGDSCR[15] reads as 0. If DBGEN is HIGH, then the read value reverts to the programmed value.

The Halting debug-mode enable bit. This is a read and write bit.

0 = Halting debug-mode disabled, reset value

1 = Halting debug-mode enabled.

If the external interface input DBGEN is LOW, DBGDSCR[14] reads as 0. If DBGEN is HIGH, then the read value reverts to the programmed value.

[13]

Execute ARM instruction enable bit. This is a read and write bit.

0 = disabled, reset value

1 = enabled.

If this bit is set and a DBGITR write succeeds, the processor fetches an instruction from the DBGITR for execution. If this bit is set to 1 when the processor is not in debug state, the behavior of the processor is Unpredictable.

[12]

CP14 user access disable

CP14 debug user access disable control bit. This is a read and write bit.

0 = CP14 debug user access enable, reset value

1 = CP14 debug user access disable.

If this bit is set and a User mode process tries to access any CP14 debug registers, the Undefined instruction exception is taken.

[11]

Interrupt disable

Interrupts disable bit. This is a read and write bit.

0 = interrupts enabled, reset value

1 = interrupts disabled.

If this bit is set, the IRQ and FIQ input signals are disabled. The external debugger can set this bit before it executes code in normal state as part of the debugging process. If this bit is set to 1, an interrupt does not take control of the program flow. For example, the debugger might use this bit to execute an OS service routine to bring a page from disk into memory. It might be undesirable to service any interrupt during the routine execution.

This bit is ignored when either:

[10]

Debug Acknowledge bit. This is a read and write bit. If this bit is set to 1, both the DBGACK and DBGTRIGGER output signals are forced HIGH, regardless of the processor state. The external debugger can use this bit if it wants the system to behave as if the processor is in debug state. Some systems rely on DBGACK to determine whether the application or debugger generates the data accesses. The reset value is 0.

[9]

RAZ on reads, SBZP on writes.

[8]

Sticky Undefined

Sticky Undefined bit:

0 = No Undefined instruction exception occurred in debug state since the last time this bit was cleared. This is the reset value.

1 = An Undefined instruction exception has occurred while in debug state since the last time this bit was cleared.

This flag detects Undefined instruction exceptions generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when an Undefined instruction exception occurs while the processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register.

Sticky asynchronous Data Abort bit:

0 = no asynchronous Aborts occurred since the last time this bit was cleared, reset value

1 = an asynchronous Abort occurred since the last time this bit was cleared.

This flag detects asynchronous Aborts triggered by instructions issued to the processor through the DBGITR. This bit is set to 1 when an asynchronous Abort occurs while the processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register.

[6]

Sticky synchronous Data Abort bit:

0 = no synchronous Data Abort occurred since the last time this bit was cleared, reset value

1 = a synchronous Data Abort occurred since the last time this bit was cleared.

This flag detects synchronous Data Aborts generated by instructions issued to the processor through the DBGITR. This bit is set to 1 when a synchronous Data Abort occurs while the processor is in debug state. Writing a 1 to DBGDRCR[2] clears this bit. See Debug Run Control Register.

When this is set, no instructions are issued through the DBGITR. Writes to DBGITR are ignored and, if ExtDCCmode is configured for Fast mode, reads of DBGDTRTXext and writes of DBGDTRRXext are ignored.

[5:2]

MOE, Method of entry bits. This is a read and write field.

b0000 = a DRCR[0] halting debug event occurred, reset value

b0001 = a breakpoint occurred

b0010 = not supported

b0011 = a BKPT instruction occurred

b0100 = an EDBGRQ halting debug event occurred

b0101 = a vector catch debug event occurred

b1010 = a synchronous watchpoint debug event occurred

other = reserved.

These bits are set to indicate any of:

A Prefetch Abort or Data Abort handler must check the value of the CP15 Fault Status Register to determine whether a debug exception occurred and then use these bits to determine the specific debug event.

[1]^a

Core restarted bit:

0 = The processor is exiting debug state.

1 = The processor has exited debug state. This is the reset value.

The debugger can poll this bit to determine when the processor responds to a request to leave debug state.

[0]^a

Core halted bit:

0 = The processor is in normal state. This is the reset value.

1 = The processor is in debug state.

The debugger can poll this bit to determine when the processor has entered debug state.