| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
 PDF version | |
| Home > Debug > Debug register descriptions > Debug State Cache Control Register |
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| Home > Debug > Debug register descriptions > Debug State Cache Control Register | |||
The DBGDSCCR controls cache behavior while the processor is in debug state. The Cortex-A5 processor does not implement any of the features of the DBGDSCCR. The DBGDSCCR is read-as-zero.
| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > Debug > Debug register descriptions > Debug State Cache Control Register |