Cortex-A5 Technical Reference ManualRevision: r0p1
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9.5.8. Debug Run Control Register

The DBGDRCR characteristics are:

Purpose

Requests the processor to enter or leave debug state. It also clears the sticky exception bits present in the DBGDSCR.

Usage constraints

There are no usage constraints.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.1.

Figure 9.5 shows the DBGDRCR bit assignments.

Figure 9.5. DBGDRCR bit assignments

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Table 9.5 shows the DBGDRCR bit assignments.

Table 9.5. DBGDRCR bit assignments

BitsNameDescription

[31:5]

Reserved

RAZ/SBZP.

[4]Cancel BIU requestImplemented.

[3]

Clear sticky pipeline advance

Clear sticky pipeline advance. Writing a 1 to this bit clears DBGDSCR[25].

[2]

Clear sticky exceptions

Clear sticky exceptions. Writing a 1 to this bit clears DBGDSCR[8:6].

[1]

Restart request

Restart request. Writing a 1 to this bit requests that the processor leaves debug state. This request is held until the processor exits debug state. When the debugger makes this request, it polls DBGDSCR[1] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is not in debug state.

[0]

Halt request

Halt request. Writing a 1 to this bit triggers a halting debug event, that is, a request that the processor enters debug state. This request is held until the debug state entry occurs. When the debugger makes this request, it polls DBGDSCR[0] until it reads 1. This bit always reads as zero. Writes are ignored when the processor is already in debug state.


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