Cortex-A5 Technical Reference Manual: 9.7.1. Processor integration testing

9.7.1. Processor integration testing

This section describes the behavior and use of the Integration Test Registers that are in the processor. It also describes the Integration Mode Control Register that controls the use of the Integration Test Registers. For more information about the DBGITCTRL see the ARM Architecture Reference Manual.

If you want to access these registers you must first set bit [0] of the Integration Mode Control Register to 1.

You can use the write-only Integration Test Registers to set the outputs of some of the processor signals. Table 9.30 shows the signals that you can write in this way.
You can use the read-only Integration Test Registers to read the state of some of the processor inputs. Table 9.31 shows the signals that you can read in this way.

Table 9.30. Output signals that can be controlled by the Integration Test Registers

Signal	Register	Bit	Register description
DBGRESTARTED	DBGITMISCOUT	[9]	See DBGITMISCOUT Register (Miscellaneous Outputs)
PMUIRQ	DBGITMISCOUT	[4]
DBGACK	DBGITMISCOUT	[0]

Table 9.31. Input signals that can be read by the Integration Test Registers

Signal	Register	Bit	Register description
DBGRESTART	DBGITMISCIN	[11]	See DBGITMISCIN Register (Miscellaneous Inputs)
nIRQ	DBGITMISCIN	[2]
nFIQ	DBGITMISCIN	[1]
EDBGRQ	DBGITMISCIN	[0]

This section describes:

Using the Integration Test Registers

When bit [0] of the Integration Mode Control Register (DBGITCTRL) is set to b1:

Values written to the write-only Integration Test Registers map onto the specified outputs of the processor. For example, writing b1 to DBGITMISCOUT[0] causes DBGACK to be asserted HIGH.
Values read from the read-only Integration Test Registers correspond to the values of the specified inputs of the processor. For example, if you read DBGITMISCIN[11] you obtain the value of DBGRESTART.

Performing integration testing

When you perform integration testing or topology detection, ARM strongly recommends that the processor is halted while in debug state, because toggling input and output pins might have an unwanted effect on the operation of the processor. You must not set the DBGITCTRL Register until the processor has halted.

After you perform integration testing or topology detection, that is, the Integration Mode Control Register has been set, the system must be reset. This is because the signals that are toggled can have an unwanted effect on connected devices.

DBGITMISCOUT Register (Miscellaneous Outputs)

The DBGITMISCOUT Register characteristics are:

Purpose

Sets the state of the output pins shown in Table 9.30.

Usage constraints

Available when bit [0] of DBGITCTRL is set to 1
The value of the register sets the signals on the output pins when the register is written.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.1.

Figure 9.16 shows the DBGITMISCOUT Register bit assignments.

Figure 9.16. DBGITMISCOUT Register bit assignments

Table 9.32 shows the DBGITMISCOUT Register bit assignments. When this register is written the appropriate output pins take the value written.

Table 9.32. DBGITMISCOUT Register bit assignments

Bits	Name	Function
[31:10]	-	Reserved. Write as zero.
[9]	DBGRESTARTED	Set value of the DBGRESTARTED output pin.
[8:5]	-	Reserved. Write as zero.
[4]	PMUIRQ	Set value of PMUIRQ output pin.
[3:1]	-	Reserved. Write as zero.
[0]	DBGACK	Set value of the DBGACK output pin.

DBGITMISCIN Register (Miscellaneous Inputs)

The DBGITMISCIN Register characteristics are:

Purpose

Reads the state of the input pins shown in Table 9.31.

Usage constraints

Available when bit [0] of DBGITCTRL is set to 1
The values of the register bits depend on the signals on the input pins when the register is read.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 9.1.

Figure 9.17 shows the DBGITMISCIN Register bit assignments.

Figure 9.17. DBGITMISCIN Register bit assignments

Table 9.33 shows the DBGITMISCIN Register bit assignments.

Table 9.33. DBGITMISCIN Register bit assignments

Bits	Name	Function
[31:12]	-	Reserved. Read Undefined.
[11]	DBGRESTART	Read value of the DBGRESTART input pin.
[10:3]	-	Reserved. Read Undefined.
[2]	nFIQ	Read value of nFIQ input pin.
[1]	nIRQ	Read value of nIRQ input pin.
[0]	EDBGRQ	Read value of EDBGRQ input pin.

Integration Mode Control Register

The DBGITCTRL Register characteristics are:

Purpose: Enables the processor to switch from a functional, default mode, into integration mode, where the inputs and outputs of the device can be directly controlled for integration testing or topology detection.
Usage constraints: There are no usage constraints.
Configurations: Available in all configurations.
Attributes: See the register summary in Table 9.1.

Figure 9.18 shows the DBGITCTRL Register bit assignments.

Figure 9.18. DBGITCTRL Register bit assignments

Table 9.34 shows the DBGITCTRL Register bit assignments.

Table 9.34. DBGITCTRL Register bit assignments

Bits	Name	Function
[31:1]	-	Reserved.
[0]	INTMODE	Controls whether the processor is in normal operating mode or integration mode: b0 = normal operation b1 = integration mode enabled.

Bits

Name

Function

[31:1]

Reserved.

[0]

INTMODE

Controls whether the processor is in normal operating mode or integration mode:

b0 = normal operation

b1 = integration mode enabled.

Writing to the DBGITCTRL register controls whether the processor is in its default functional mode, or in integration mode, where the inputs and outputs of the device can be directly controlled for the purpose of integration testing or topology detection. For more information see the ARM Architecture Reference Manual.

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