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In the optional Cortex-A5 implementation of the Jazelle Extension:
Jazelle state is supported.
The BXJ instruction enters Jazelle
state.
Table 5.1 shows the CP14 Jazelle registers. All Jazelle registers are 32 bits wide.
Table 5.1. CP14 Jazelle registers summary
| CRn | Op1 | CRm | Op2 | Name | Type | Reset | Description |
|---|---|---|---|---|---|---|---|
| 0 | 7 | 0 | 0 | JIDR | RW[a] |
| Jazelle Identity and Miscellaneous Functions Register |
| 7 | 1 | 0 | 0 | JOSCR | RW | - | Jazelle Operating System Control Register |
| 7 | 2 | 0 | 0 | JMCR | RW | - | Jazelle Main Configuration Register |
| 7 | 3 | 0 | 0 | JPR | RW | - | Jazelle Parameters Register |
| 7 | 4 | 0 | 0 | JCOTTR | WO | - | Jazelle Configurable Opcode Translation Table Register |
[a] See Write operation of the JIDR for the effect of a write operation | |||||||
See the ARM Architecture Reference Manual for details of the Jazelle Extension.
| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > Non-debug Use of CP14 > CP14 Jazelle register summary |