| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
 PDF version | |
| Home > Functional Description > About the functions > Instruction side memory system |
| |||
| Home > Functional Description > About the functions > Instruction side memory system | |||
The instruction side memory system is described in:
The Instruction Cache Unit (ICU) contains the Instruction Cache controller and its associated linefill buffer. The Cortex-A5 ICache is two-way set associative and uses Virtually Indexed Physically Tagged (VIPT) cache-lines holding up to eight ARM or up to sixteen Thumb instructions.
The Prefetch Unit (PFU) obtains instructions from the instruction cache or from external memory and predicts the outcome of branches in the instruction stream, then passes the instructions to the DPU for processing. In any given cycle, up to a maximum of four instructions can be fetched and two can be passed to the DPU.
The PFU also contains a small four-entry deep Branch Target Address Cache (BTAC) used to predict the target address of certain indirect branches. The BTAC implementation is architecturally transparent, so it does not have to be flushed on a context switch.
The branch predictor is a global type that uses history registers and a 256-entry pattern history table.
The PFU includes a 4-entry return stack to accelerate returns from procedure calls. For each procedure call, the return address is pushed onto a hardware stack. When a procedure return is recognized, the address held in the return stack is popped, and the PFU uses it as the predicted return address. The return stack is architecturally transparent, so it does not have to be flushed on a context switch
| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > Functional Description > About the functions > Instruction side memory system |