Cortex-A5 Technical Reference ManualRevision: r0p1
Home > System Control > Register descriptions > Debug Feature Register 0

4.3.8. Debug Feature Register 0

The ID_DFR0 characteristics are:

Purpose

Provides information about the debug system for the processor.

Usage constraints

The ID_DFR0 is:

  • only accessible in privileged modes

  • common to the Secure and Non-secure states.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.9.

Figure 4.12 shows the ID_DFR0 bit assignments.

Figure 4.12. ID_DFR0 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Table 4.27 shows the ID_DFR0 bit assignments.

Table 4.27. ID_DFR0 bit assignments

BitsNameDescription
[31:28]ReservedRAZ.
[27:24]Performance monitors model0x2 Version 2.
[23:20]Debug model, M profile

0x0 Not supported.

[19:16]Memory-mapped trace model

0x1 Memory-mapped trace debug model supported.

[15:12]Coprocessor trace model

0x0 Not supported.

[11:8]Memory-mapped debug model

0x4 Memory-mapped core debug model supported.

[7:4]Coprocessor Secure debug model0x4 Coprocessor based secure debug model supported using CP14.
[3:0]Coprocessor debug model0x4 Coprocessor based core debug model supported supported using CP14.

To access ID_DFR0, use:

MRC p15, 0, <Rd>, c0, c1, 2

Copyright © 2009, 2010 ARM. All rights reserved.ARM DDI 0433B
Non-ConfidentialID101810
PDF file icon  PDF version
Home > System Control > Register descriptions > Debug Feature Register 0