Cortex-A5 Technical Reference ManualRevision: r0p1
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4.3.12. Memory Model Features Register 2

The ID_MMFR2 characteristics are:

Purpose

Provides information about the memory model, memory management, cache support, and TLB operations of the processor.

Usage constraints

The ID_MMFR2 is:

  • only accessible in privileged modes

  • common to the Secure and Non-secure states.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.9.

Figure 4.15 shows the ID_MMFR2 bit assignments.

Figure 4.15. ID_MMFR2 bit assignments

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Table 4.31 shows the ID_MMFR2 bit assignments.

Table 4.31. ID_MMFR2 bit assignments

BitsNameDescription
[31:28]HW access flag

0x0 Not supported.

[27:24]WFI stall

0x1 Wait For Interrupt (WFI) supported.

[23:20]Mem barrier

0x2 Supports:

  • Data Synchronization Barrier (DSB)

  • Instruction Synchronization Barrier (ISB)

  • Data Memory Barrier (DMB).

[19:16]Unified TLB

0x3 Supports:

  • invalidate all entries

  • invalidate TLB entry by VA

  • invalidate TLB entries by ASID match.

[15:12]Harvard TLB

0x0 Not supported.

[11:8]L1 Harvard range

0x0 Not supported.

[7:4]L1 Harvard background prefetch

0x0 Not supported.

[3:0]L1 Harvard foreground prefetch

0x0 Not supported.


To access the ID_MMFR2 use:

MRC p15, 0, <Rd>, c0, c1, 6
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