| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
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The VIR characteristics are:
Triggers a pending interrupt from software running on the processor.
The VIR is:
only accessible in privileged modes
common to Secure and Non-secure state.
Available in all configurations.
See the register summary in Table 4.19.
Figure 4.43 shows the VIR bit assignments.
Table 4.64 shows the VIR bit assignments.
Table 4.64. VIR bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:9] | Reserved | RAZ/WI. |
| [8] | VA | Virtual Abort bit. When set the virtual abort becomes pending when SCR.EA and VCR.AMO are b1. The virtual abort exception happens only when the processor is in Non-secure state and the CPSR.A field is clear. |
| [7] | VI | Virtual IRQ bit. When set the virtual interrupt becomes pending when SCR.IRQ and VCR.IMO are b1. The virtual interrupt exception happens only when the processor is in Non-secure state and the CPSR.I field is clear. |
| [6] | VF | Virtual FIQ bit. When set the virtual interrupt becomes pending when SCR.FIQ and VCR.FMO are b1. The virtual interrupt exception happens only when the processor is in Non-secure state and the CPSR.F field is clear. |
| [5:0] | Reserved | RAZ/WI. |
To access the VIR, use:
MRC p15, 0, <Rd>, c12, c1, 1 ; Read VIR Register
MCR p15, 0, <Rd>, c12, c1, 1 ; Write VIR Register
A virtual abort or interrupt becomes pending when the associated abort/interrupt field in the SCR {EA, IRQ, FIQ} is set and the appropriate VCR mask override field in the VCR {AMO, IMO, FMO} is also set. The actual virtual interrupt/abort exception is taken only when the CPU enters Non-secure state and can be masked using the CPSR {A,I,F} fields.
When a virtual abort is taken, the corresponding bit in the VIR is cleared automatically by hardware. When a virtual interrupt is taken, the corresponding bit in the VIR is not changed by hardware. For the purposes of WFE and WFI, virtual interrupts and aborts are treated in the same way as normal interrupts and aborts.
| Copyright © 2009, 2010 ARM. All rights reserved. | ARM DDI 0433B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > System Control > Register descriptions > Virtualization Interrupt Register |