Cortex-A5 Technical Reference Manual: 4.3.33. Translation Table Base Register 1

4.3.33. Translation Table Base Register 1

The TTBR1 characteristics are:

Purpose

Holds the physical address of the first-level translation table.

Usage constraints

The TTBR1 is:

only accessible in privileged modes
banked for Secure and Non-secure states.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.11.

Figure 4.33 shows the TTBR1 bit assignments.

Figure 4.33. TTBR1 bit assignments

Table 4.55 shows the TTBR1 bit assignments.

Table 4.55. TTBR1 bit assignments

Bits	Name	Description
[31:14]	Translation table base 1	Pointer to the level one translation table.
[13:7]	Reserved	UNP or SBZ
[6]	IRGN[0]	Used with IRGN[1] to describe inner cacheability.
[5]	Reserved	RAZ/WI
[4:3]	RGN	Outer cacheable attributes for translation table walking: b00 = Outer Non-cacheable b01 = Outer Cacheable Write-Back cached, Write-Allocate b10 = Outer Cacheable Write-Through, no allocate on write b11 = Outer Cacheable write-back, no allocate on write.
[2]	Reserved	SBZ
[1]	S	Translation table walk: 1 = to shared memory 0 = to non-shared memory.
[0]	IRGN[1]	Indicates inner cacheability for the translation table walk: IRGN[1], IRGN[0] 00 = Non-cacheable 01 = Write-Back Write-Allocate 10 = Write-Through, no allocate on write 11 = Write-Back no allocate on write. Page table walks do look-ups in the data cache only in write-back. Write-through is treated as non-cacheable.

To access TTBR1, use:

MRC p15, 0, <Rd>, c2, c0, 1; Read TTBR1

MCR p15, 0, <Rd>, c2, c0, 1; Write TTBR1

Writing to CP15 c2 updates the pointer to the first level translation table from the value in bits [31:14] of the written value. Bits [13:7] Should Be Zero. The address specified by TTBR1 must reside on a 16KB page boundary.

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