Cortex-A5 Technical Reference ManualRevision: r0p1
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10.2.12. User Enable Register

The PMUSERENR characteristics are:

Purpose

Enables user mode to have access to the Performance Monitor Registers.

Usage constraints

The PMUSERENR is:

  • writable only in privileged modes and readable in any processor mode.

  • common to Secure and Non-secure states.

Note

The PMUSERENR does not provide access to the registers that control interrupt generation.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.17.

Figure 10.9 shows the PMUSERENR bit assignments.

Figure 10.9. PMUSERENR bit assignments

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Table 10.13 shows the PMUSERENR bit assignments.

Table 10.13. PMUSERENR bit assignments

BitsNameDescription
[31:1]ReservedRAZ/SBZP
[0]ENUser mode enable. 0 is the reset value

To access the PMUSERENR, use:

MRC p15, 0,<Rd>, c9, c14, 0 ; Read PMUSERENR

MCR p15, 0,<Rd>, c9, c14, 0 ; Write PMUSERENR
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