Cortex-A5 Technical Reference Manual: 5.3.2. Jazelle Operating System Control Register

The JOSCR characteristics are:

Purpose

Enables operating systems to control access to Jazelle Extension hardware.

Usage constraints

The JOSCR is:

Configurations

Available in all configurations.

Attributes

See the register summary in Table 5.1.

Figure 5.2 shows the JOSCR bit assignments.

Figure 5.2. JOSCR bit assignments

Table 5.3 shows the JOSCR bit assignments.

Table 5.3. JOSCR bit assignments

Bits	Name	Description
[31:2]	Reserved	SBZ.
[1]	CV	Configuration Valid bit. 0 = The Jazelle configuration is invalid. Any attempt to enter Jazelle state when the Jazelle hardware is enabled: generates a configuration invalid Jazelle exception sets this bit, marking the Jazelle configuration as valid. 1 = The Jazelle configuration is valid. Entering Jazelle state succeeds when the Jazelle hardware is enabled. The CV bit is automatically cleared on an exception.
[0]	CD	Configuration Disabled bit. 0 = Jazelle configuration in User mode is enabled: reading the JIDR succeeds reading any other Jazelle configuration register generates an Undefined Instruction exception writing the JOSCR generates an Undefined Instruction exception writing any other Jazelle configuration register succeeds. 1 = Jazelle configuration from User mode is disabled: reading any Jazelle configuration register generates an Undefined Instruction exception writing any Jazelle configuration register generates an Undefined Instruction exception.

Bits

Name

Description

[31:2]

Reserved

SBZ.

[1]

Configuration Valid bit.

0 = The Jazelle configuration is invalid. Any attempt to enter Jazelle state when the Jazelle hardware is enabled:

1 = The Jazelle configuration is valid. Entering Jazelle state succeeds when the Jazelle hardware is enabled.

The CV bit is automatically cleared on an exception.

[0]

Configuration Disabled bit.

0 = Jazelle configuration in User mode is enabled:

reading the JIDR succeeds
reading any other Jazelle configuration register generates an Undefined Instruction exception
writing the JOSCR generates an Undefined Instruction exception
writing any other Jazelle configuration register succeeds.

1 = Jazelle configuration from User mode is disabled:

reading any Jazelle configuration register generates an Undefined Instruction exception
writing any Jazelle configuration register generates an Undefined Instruction exception.

To access the JOSCR, use:

MRC p14, 7, <Rd>, c1, c0, 0 ; Read JOSCR

MCR p14, 7. <Rd>, c1, c0, 0 ; Write JOSCR

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