Cortex-A5 Technical Reference Manual: A.1.6. AXI interfaces

A.1.6. AXI interfaces

The following sections describe the AXI interface signals:

Write address channel signals

Table A.6 shows the AXI write address channel signals.

Table A.6. AXI write address channel signals

Name	Type	Description
AWADDR[31:0]	Output	Address.
AWBURST[1:0]	Output	Burst type: b01 = INCR incrementing burst b10 = WRAP wrapping burst. All other values are reserved.
AWCACHE[3:0]	Output	Cache type giving additional information about outer cacheable characteristics: b0000 = Strongly-ordered b0001 = Device b0011 = Normal, Non-Cacheable b0110 = Normal, Write-Through, no Write-Allocate b0111 = Normal, Write-Back, no Write-Allocate b1111 = Normal, Write-Back, Write-Allocate,
AWID[1:0]	Output	Request ID.
AWLEN[3:0]	Output	Number of data transfers that can occur in each burst. Each burst can be 1-16 transfers long: b0000 = 1 data transfer b0001 = 2 data transfers b0010 = 3 data transfers b0011 = 4 data transfers . . . b1111 = 16 data transfers.
AWLOCK[1:0]	Output	Lock type: b00 = normal access b01 = exclusive access b1x = not used.
AWPROT[2:0]	Output	Protection type.
AWREADY	Input	Address ready.
AWSIZE[2:0]	Output	Burst size: b000 = 8-bit transfer b001 = 16-bit transfer b010 = 32-bit transfer b011 = 64-bit transfer.
AWUSER[6:0]	Output	[6:5] Exclusive mode: b00 = Not an eviction b01 = An eviction with dirty data b10 = Not used b11 = An eviction but the data is clean [4:0] Inner attributes: b00001 = Strongly ordered b00010 = Device, non-shareable b00011 = Device, shareable b00110 = Non-cacheable, non-shareable b00111 = Non-cacheable, shareable b11110 = Writeback cacheable, read and write allocate, non-shareable b11111 = Writeback cacheable, read and write allocate, shareable
AWVALID	Output	Address valid.

Write data channel signals

Table A.7 shows the AXI write data channel signals.

Table A.7. AXI write data channel signals

Name	Type	Description
WDATA[63:0]	Output	Write data.
WID[1:0]	Output	Write ID.
WLAST	Output	Write last indication.
WREADY	Input	Write ready.
WSTRB[7:0]	Output	Write byte lane strobe.
WVALID	Output	Write valid.

Write data response channel signals

Table A.8 shows the AXI write data response channel signals.

Table A.8. AXI write data response channel signals

Name	Type	Description
BID[1:0]	Input	Response ID.
BREADY	Output	Response ready.
BRESP[1:0]	Input	Write response.
BVALID	Input	Response valid.

Read address channel signals

Table A.9 shows the AXI read address channel signals.

Table A.9. AXI read address channel signals

Name	Type	Description
ARADDR[31:0]	Output	Address.
ARBURST[1:0]	Output	Burst type: b01 = INCR incrementing burst b10 = WRAP wrapping burst. All other values are reserved.
ARCACHE[3:0]	Output	Cache type giving additional information about outer cacheable characteristics: b0000 = Strongly-ordered b0001 = Device b0011 = Normal, Non-Cacheable b0110 = Normal, Write-Through, no Write-Allocate b0111 = Normal, Write-Back, no Write-Allocate b1111 = Normal, Write-Back, Write-Allocate.
ARID[2:0]	Output	Request ID.
ARLEN[3:0]	Output	Number of data transfers that can occur in each burst. Each burst can be 1-16 transfers long: b0000 = 1 data transfer b0001 = 2 data transfers b0010 = 3 data transfers b0011 = 4 data transfers . . . b1111 = 16 data transfers.
ARLOCK[1:0]	Output	Lock type: b00 = normal access b01 = exclusive access b10 = locked access.
ARPROT[2:0]	Output	Protection type.
ARREADY	Input	Address ready.
ARSIZE[2:0]	Output	Burst size: b000 = 8-bit transfer b001 = 16-bit transfer b010 = 32-bit transfer b011 = 64-bit transfer.
ARUSER[4:0]	Output	Inner attributes: b00001 = Strongly ordered b00010 = Device, non-shareable b00011 = Device, shareable b00110 = Non-cacheable, non-shareable b00111 = Non-cacheable, shareable b11110 = Writeback cacheable, read and write allocate, non-shareable b11111 = Writeback cacheable, read and write allocate, shareable
ARVALID	Output	Address valid.

Read data channel signals

Table A.10 shows the AXI read data signals.

Table A.10. AXI read data signals

Name	Type	Description
RVALID	Input	Read valid.
RDATA[63:0]	Input	Read data.
RRESP[1:0]	Input	Read response.
RLAST	Input	Read last.
RID[2:0]	Input	Read ID.
RREADY	Output	Read ready.

AXI clock enable signal

Table A.11 shows the AXI clock enable signal.

Table A.11. AXI clock enable signal

Name	Type	Description
ACLKEN	Input	Master AXI bus clock enable.

See Clocking.

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