Cortex-A5 Technical Reference ManualRevision: r0p1
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4.3.7. Processor Feature Register 1

The ID_PFR1 characteristics are:

Purpose

Provides information about the execution state support and programmers model for the processor.

Usage constraints

The ID_PFR1 is:

  • only accessible in privileged modes

  • common to the Secure and Non-secure states.

The ID_PFR1 must be interpreted with ID_PFR0.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.9.

Figure 4.11 shows the ID_PFR1 Register bit assignments.

Figure 4.11. ID_PFR1 bit assignments

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Table 4.26 shows the ID_PFR1 bit assignments.

Table 4.26. ID_PFR1 bit assignments

BitsNameDescription
[31:12]ReservedRAZ.
[11:8]M profile programmers model

0x0 Not supported.

[7:4]Security extensions0x1 Security extension architecture v1 supported.
[3:0]Programmers model0x1 standard ARMv4 programmers model supported.

To access ID_PFR1, use:

MRC p15, 0, <Rd>, c0, c1, 1

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