Cortex-A5™ Technical Reference Manual

Revision: r0p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
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1. Introduction
1.1. About the Cortex-A5 processor
1.1.1. Floating-Point Unit
1.1.2. Media Processing Engine
1.1.3. System design components
1.2. Variants
1.3. Compliance
1.4. Features
1.5. Interfaces
1.6. Configurable options
1.7. Test features
1.8. Product documentation, design flow, and architecture
1.8.1. Documentation
1.8.2. Design flow
1.8.3. Architecture and protocol information
1.9. Product revisions
2. Functional Description
2.1. About the functions
2.1.1. Data Processing Unit
2.1.2. System control coprocessor
2.1.3. Instruction side memory system
2.1.4. Data side memory system
2.1.5. L1 memory system
2.1.6. L2 AXI interfaces
2.1.7. Media Processing Engine
2.1.8. Floating-Point Unit
2.1.9. Debug
2.1.10. Performance monitoring
2.1.11. Virtualization extensions
2.2. Interfaces
2.2.1. ETM interface
2.3. Clocking and resets
2.3.1. Clocking
2.3.2. Resets
2.4. Power management
2.4.1. Power control
2.4.2. Power domains
2.4.3. Communication to the Power Management Controller
2.4.4. IEM support
3. Programmers Model
3.1. About the programmers model
3.2. Jazelle extension
3.3. NEON technology
3.4. Processor operating states
3.4.1. Switching state
3.4.2. Interworking ARM and Thumb code sequences
3.5. Data types
3.6. Memory formats
3.7. Addresses in the Cortex-A5 processor
3.8. Security Extensions overview
3.8.1. System boot sequence
3.8.2. Security Extensions write access disable
4. System Control
4.1. About system control
4.1.1. System control functional groups
4.1.2. System control and configuration
4.1.3. MMU control and configuration
4.1.4. Cache control and configuration
4.1.5. Cache Operations Registers
4.1.6. System performance monitor registers
4.1.7. System feature registers
4.1.8. c0, Instruction set attributes registers
4.1.9. c7, VA to PA operations
4.1.10. c8, TLB maintenance operations
4.1.11. c10, Memory region remap
4.1.12. c13, Software Thread ID Registers
4.1.13. c15, TLB access and attributes
4.2. Register summary
4.2.1. Virtualization
4.2.2. c0 summary table
4.2.3. c1 summary table
4.2.4. c2 summary table
4.2.5. c3 summary table
4.2.6. c4 summary table
4.2.7. c5 summary table
4.2.8. c6 summary table
4.2.9. c7 summary table
4.2.10. c8 summary table
4.2.11. c9 summary table
4.2.12. c10 summary table
4.2.13. c11 summary table
4.2.14. c12 summary table
4.2.15. c13 summary table
4.2.16. c14 summary table
4.2.17. c15 summary table
4.3. Register descriptions
4.3.1. Main ID Register
4.3.2. Cache Type Register
4.3.3. TCM Type Register
4.3.4. TLB Type Register
4.3.5. Multiprocessor Affinity Register
4.3.6. Processor Feature Register 0
4.3.7. Processor Feature Register 1
4.3.8. Debug Feature Register 0
4.3.9. Auxiliary Feature Register 0
4.3.10. Memory Model Features Register 0
4.3.11. Memory Model Features Register 1
4.3.12. Memory Model Features Register 2
4.3.13. Memory Model Features Register 3
4.3.14. Instruction Set Attributes Register 0
4.3.15. Instruction Set Attributes Register 1
4.3.16. Instruction Set Attributes Register 2
4.3.17. Instruction Set Attributes Register 3
4.3.18. Instruction Set Attributes Register 4
4.3.19. Instruction Set Attributes Register 5
4.3.20. Instruction Set Attributes Registers 6-7
4.3.21. Cache Size Identification Register
4.3.22. Cache Level ID Register
4.3.23. Auxiliary ID Register
4.3.24. Cache Size Selection Register
4.3.25. System Control Register
4.3.26. Auxiliary Control Register
4.3.27. Coprocessor Access Control Register
4.3.28. Secure Configuration Register
4.3.29. Secure Debug Enable Register
4.3.30. Non-secure Access Control Register
4.3.31. Virtualization Control Register
4.3.32. Translation Table Base Register 0
4.3.33. Translation Table Base Register 1
4.3.34. Translation Table Base Control Register
4.3.35. Domain Access Control Register
4.3.36. Data Fault Status Register
4.3.37. Instruction Fault Status Register
4.3.38. Auxiliary Data Fault Status Register
4.3.39. Auxiliary Instruction Fault Status Register
4.3.40. Data Fault Address Register
4.3.41. Instruction Fault Address Register
4.3.42. NOP Register
4.3.43. Physical Address Register
4.3.44. Instruction Synchronization Barrier
4.3.45. Data Synchronization Barrier
4.3.46. Data Memory Barrier
4.3.47. Vector Base Address Register
4.3.48. Monitor Vector Base Address Register
4.3.49. Interrupt Status Register
4.3.50. Virtualization Interrupt Register
4.3.51. Context ID Register
4.3.52. Configuration Base Address Register
5. Non-debug Use of CP14
5.1. About coprocessor CP14
5.2. CP14 Jazelle register summary
5.3. CP14 Jazelle register descriptions
5.3.1. Jazelle Identity and Miscellaneous Functions Register
5.3.2. Jazelle Operating System Control Register
5.3.3. Jazelle Main Configuration Register
5.3.4. Jazelle Parameters Register
5.3.5. Jazelle Configurable Opcode Translation Table Register
6. Memory Management Unit
6.1. About the MMU
6.2. Memory management system
6.2.1. Memory types
6.3. TLB organization
6.3.1. Micro TLB
6.3.2. Main TLB
6.4. Memory access sequence
6.5. Interaction with memory system
6.6. External aborts
6.6.1. External aborts on data write
6.6.2. Synchronous and asynchronous aborts
6.7. MMU software accessible registers
7. Level 1 Memory System
7.1. About the L1 memory system
7.1.1. Memory system
7.2. Security extensions support
7.3. L1 instruction side memory system
7.3.1. Enabling program flow prediction
7.3.2. Program flow prediction
7.4. L1 data side memory system
7.4.1. Internal exclusive monitor
7.4.2. External aborts handling
7.5. Data prefetching
7.5.1. The PLD instruction
7.5.2. Data prefetching and monitoring
7.6. Direct access to internal memory
7.6.1. Data Cache Tag and Data encoding
7.6.2. Instruction Cache Tag and Data encoding
7.6.3. TLB data encoding
8. Level 2 Memory Interface
8.1. About the L2 interface
8.1.1. AXI master interface
8.1.2. L2 memory interface attributes
8.1.3. Supported AXI transfers
8.1.4. AXI transaction IDs
8.1.5. AXI user bits
8.1.6. Write response
8.1.7. Exclusive L2 cache
8.2. AXI privilege information
9. Debug
9.1. About debug
9.1.1. Debug host
9.1.2. Protocol converter
9.1.3. Debug target
9.1.4. About the debug unit
9.2. Debugging modes
9.2.1. Halting debug-mode debugging
9.2.2. Monitor debug-mode debugging
9.2.3. Performance monitor and events
9.2.4. Security extensions and debugging
9.3. Debug interface
9.3.1. Breakpoints and watchpoints
9.3.2. Asynchronous aborts
9.3.3. Processor interfaces
9.3.4. Effects of resets on debug registers
9.4. Debug register summary
9.5. Debug register descriptions
9.5.1. Debug Identification Register
9.5.2. Debug Status and Control Register
9.5.3. Program Counter Sampling Register
9.5.4. Debug State Cache Control Register
9.5.5. Event Catch Register
9.5.6. Debug State MMU Control Register
9.5.7. Operating System Lock and Save/Restore Registers
9.5.8. Debug Run Control Register
9.5.9. Breakpoint Value Registers
9.5.10. Breakpoint Control Registers
9.5.11. Watchpoint Value Register
9.5.12. Watchpoint Control Register
9.5.13. Device Power-down and Reset Control Register
9.5.14. Device Power-down and Reset Status Register
9.6. Management registers
9.6.1. Processor ID Registers
9.6.2. Claim Tag Set Register
9.6.3. Claim Tag Clear Register
9.6.4. Lock Access Register
9.6.5. Lock Status Register
9.6.6. Authentication Status Register
9.6.7. Device Type Register
9.6.8. Identification Registers
9.7. Integration test registers
9.7.1. Processor integration testing
9.8. External debug interface
9.9. Miscellaneous debug signals
9.9.1. EDBGRQ
9.9.2. DBGACK
9.9.3. COMMRX and COMMTX
9.9.4. Memory mapped accesses, DBGROMADDR, and DBGSELFADDR
9.9.5. Authentication signals
9.9.6. Changing the authentication signals
10. Performance Monitoring Unit
10.1. About the Performance Monitoring Unit
10.2. Performance monitoring register descriptions
10.2.1. Performance Monitor Control Register
10.2.2. Count Enable Set Register
10.2.3. Count Enable Clear Register
10.2.4. Overflow Flag Status Register
10.2.5. Software Increment Register
10.2.6. Event Counter Selection Register
10.2.7. Common Event Identification Registers
10.2.8. Cycle Count Register
10.2.9. Event Type Select Register
10.2.10. Cycle Count Filter Control Register
10.2.11. Event Count Registers
10.2.12. User Enable Register
10.2.13. Interrupt Enable Set Register
10.2.14. Interrupt Enable Clear Register
10.2.15. Configuration Register
10.2.16. Lock Access Register
10.2.17. Lock Status Register
10.2.18. Authentication Status Register
10.2.19. Device Type Register
10.2.20. Identification Registers
A. Signal Descriptions
A.1. Signal descriptions
A.1.1. Clock and reset signals
A.1.2. Interrupt signals
A.1.3. Configuration signals
A.1.4. Standby and wait for event signals
A.1.5. Power management signals
A.1.6. AXI interfaces
A.1.7. Performance monitoring signals
A.1.8. MBIST interface
A.1.9. Scan test signals
A.1.10. External debug interface
A.1.11. Trace interface signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
2.1. Cortex-A5 processor top-level diagram
2.2. ETM interface signals
2.3. Power domains
4.1. Set/Way bit assignments
4.2. CP15 Register c7 VA bit assignments
4.3. VA to PA register bit assignments
4.4. TLB Operations Register Virtual Address bit assignments
4.5. TLB Operations Register ASID bit assignments
4.6. Thread ID register bit assignments
4.7. MIDR bit assignments
4.8. CTR bit assignments
4.9. MPIDR bit assignments
4.10. ID_PFR0 bit assignments
4.11. ID_PFR1 bit assignments
4.12. ID_DFR0 bit assignments
4.13. ID_MMFR0 bit assignments
4.14. ID_MMFR1 bit assignments
4.15. ID_MMFR2 bit assignments
4.16. ID_MMFR3 bit assignments
4.17. ID_ISAR0 bit assignments
4.18. ID_ISAR1 bit assignments
4.19. ID_ISAR2 bit assignments
4.20. ID_ISAR3 bit assignments
4.21. ID_ISAR4 bit assignments
4.22. CCSIDR bit assignments
4.23. CLIDR bit assignments
4.24. CSSELR bit assignments
4.25. SCTLR bit assignments
4.26. ACTLR bit assignments
4.27. CPACR bit assignments
4.28. SCR bit assignments
4.29. SDER bit assignments
4.30. NSACR bit assignments
4.31. VCR bit assignments
4.32. TTBR0 bit assignments
4.33. TTBR1 bit assignments
4.34. TTBCR bit assignments
4.35. DACR bit assignments
4.36. DFSR bit assignments
4.37. IFSR bit assignments
4.38. PAR aborted translation bit assignments
4.39. PAR successful translation bit assignments
4.40. VBAR bit assignments
4.41. MVBAR bit assignments
4.42. ISR bit assignments
4.43. VIR bit assignments
4.44. CONTEXTIDR bit assignments
5.1. JIDR bit assignment
5.2. JOSCR bit assignments
5.3. JMCR bit assignments
5.4. JPR bit assignments
5.5. JCOTTR bit assignments
9.1. Typical debug system
9.2. DBGDIDR bit assignments
9.3. DBGDSCR bit assignments
9.4. DBGPCSR bit assignments
9.5. DBGDRCR bit assignments
9.6. DBGBCR bit assignments
9.7. DBGWCR bit assignments
9.8. DBGPRCR bit assignments
9.9. DBGPRSR bit assignments
9.10. DBGCLAIMSET Register bit assignments
9.11. DBGCLAIMCLR bit assignments
9.12. DBGLAR bit assignments
9.13. DBSLSR bit assignments
9.14. DBGAUTHSTATUS Register bit assignments
9.15. DBGDEVTYPE Register bit assignments
9.16. DBGITMISCOUT Register bit assignments
9.17. DBGITMISCIN Register bit assignments
9.18. DBGITCTRL Register bit assignments
9.19. External debug interface signals
10.1. PMCR bit assignments
10.2. PMCNTENSET Register bit assignments
10.3. PMCNTENCLR Register bit assignments
10.4. PMSOVSR bit assignments
10.5. PMSWINC Register bit assignments
10.6. PMSELR bit assignments
10.7. PMXEVTYPER bit assignments
10.8. PMCCFILTR bit assignments
10.9. PMUSERENR bit assignments
10.10. PMINTENSET Register bit assignments
10.11. PMINTENCLR Register bit assignments
10.12. PMCFGR bit assignments
10.13. PMLAR bit assignments
10.14. PMLSR bit assignments
10.15. PMAUTHSTATUS Register bit assignments
10.16. PMDEVTYPE Register bit assignments

List of Tables

1.1. Configurable options for the Cortex-A5 processor
2.1. Supported power configurations
3.1. CPSR J and T bit encoding
4.1. System registers affected by CP15SDISABLE
4.2. Cache operation functions
4.3. Set/Way bit assignments
4.4. Cache size and S parameter dependency
4.5. TLB Operations Register instructions
4.6. Primary remapping encodings
4.7. Inner or outer region type encodings
4.8. TLBHR data format
4.9. c0 system control registers
4.10. c1 system control registers
4.11. c2 system control registers
4.12. c3 system control register
4.13. c5 system control registers
4.14. c6 system control registers
4.15. c7 system control registers
4.16. c8 system control register
4.17. c9 system control registers
4.18. c10 system control registers
4.19. c12 system control registers
4.20. c13 system control registers
4.21. c15 system control registers
4.22. MIDR bit assignments
4.23. CTR bit assignments
4.24. MPIDR bit assignments
4.25. ID_PFR0 bit assignments
4.26. ID_PFR1 bit assignments
4.27. ID_DFR0 bit assignments
4.28. ID_AFR0 bit assignments
4.29. ID_MMFR0 bit assignments
4.30. ID_MMFR1 bit assignments
4.31. ID_MMFR2 bit assignments
4.32. ID_MMFR3 bit assignments
4.33. ID_ISAR0 bit assignments
4.34. ID_ISAR1 bit assignments
4.35. ID_ISAR2 bit assignments
4.36. ID_ISAR3 bit assignments
4.37. ID_ISAR4 bit assignments
4.38. ID_ISAR5 bit assignments
4.39. CCSIDR bit assignments
4.40. CLIDR bit assignments
4.41. AIDR bit assignments
4.42. CSSELR bit assignments
4.43. SCTLR bit assignments
4.44. ACTLR bit assignments
4.45. CPACR bit assignments
4.46. Results of access to the CPACR
4.47. SCR bit assignments
4.48. Operation of the SCR FW and FIQ bits
4.49. Operation of the SCR AW and EA bits
4.50. SDER bit assignments
4.51. NSACR bit assignments
4.52. Results of access to the NSACR
4.53. VCR bit assignments
4.54. TTBR0 bit assignments
4.55. TTBR1 bit assignments
4.56. TTBCR bit assignments
4.57. DACR bit assignments
4.58. DFSR bit assignments
4.59. IFSR bit assignments
4.60. PAR bit assignments
4.61. VBAR bit assignments
4.62. MVBAR bit assignments
4.63. ISR bit assignments
4.64. VIR bit assignments
4.65. CONTEXTIDR bit assignments
5.1. CP14 Jazelle registers summary
5.2. JIDR bit assignments
5.3. JOSCR bit assignments
5.4. JMCR bit assignments
5.5. Jazelle Parameters Register bit assignments
5.6. JCOTTR bit assignments
6.1. Treatment of memory attributes
6.2. CP15 register functions
7.1. Cortex-A5 system coprocessor CP15 registers used to access internal memory
7.2. Data Cache Tag and Data location encoding
7.3. Data Cache Tag data format
7.4. Instruction Cache Tag and Data location encoding
7.5. Instruction Cache Tag data format
7.6. TLB Data Read Operation Register location encoding
7.7. TLB descriptor format
8.1. AXI master interface attributes
8.2. AXI ID signal encodings
8.3. ARUSER[4:0] encodings
8.4. AWUSER[6:0] encodings
8.5. Cortex-A5 mode and APROT values
9.1. Debug interface registers
9.2. DBGDIDR bit assignments
9.3. DBGDSCR bit assignments
9.4. DBGPCSR bit assignments
9.5. DBGDRCR bit assignments
9.6. DBGBVRs and corresponding DBGBCRs
9.7. DBGBVR bit assignments
9.8. DBGBCR bit assignments
9.9. Meaning of DBGBVR bits [22:20]
9.10. WVR and corresponding WCR
9.11. DBGWVR bit assignments
9.12. DBGWCR bit assignments
9.13. DBGPRCR bit assignments
9.14. DBGPRSR bit assignments
9.15. Management registers
9.16. Processor Identifier Registers
9.17. DBGCLAIMSET Register bit assignments
9.18. DBGCLAIMCLR bit assignments
9.19. DBGLAR bit assignments
9.20. DBGLSR bit assignments
9.21. DBGAUTHSTATUS Register bit assignments
9.22. DBGDEVTYPE Register bit assignments
9.23. Peripheral Identification Registers
9.24. Peripheral ID Register 0 bit assignments
9.25. Peripheral ID Register 1 bit assignments
9.26. Peripheral ID Register 2 bit assignments
9.27. Peripheral ID Register 3 bit assignments
9.28. Peripheral ID Register 4 bit assignments
9.29. Component Identification Registers
9.30. Output signals that can be controlled by the Integration Test Registers
9.31. Input signals that can be read by the Integration Test Registers
9.32. DBGITMISCOUT Register bit assignments
9.33. DBGITMISCIN Register bit assignments
9.34. DBGITCTRL Register bit assignments
9.35. Authentication signal restrictions
10.1. Performance monitoring instructions and APB mapping
10.2. PMCR bit assignments
10.3. PMCNTENSET Register bit assignments
10.4. PMCNTENCLR Register bit assignments
10.5. PMSOVSR Register bit assignments
10.6. PMSWINC Register bit assignments
10.7. PMSELR bit assignments
10.8. PMCEID0 Register bit assignments
10.9. PMXEVTYPER bit assignments
10.10. Performance monitor events
10.11. PMCCFILTR bit assignments
10.12. Signal settings for the PMXEVCNTR
10.13. PMUSERENR bit assignments
10.14. PMINTENSET Register bit assignments
10.15. PMINTENCLR Register bit assignments
10.16. PMCFGR bit assignments
10.17. PMLAR bit assignments
10.18. PMLSR bit assignments
10.19. PMAUTHSTATUS Register bit assignments
10.20. PMDEVTYPE Register bit assignments
10.21. Peripheral Identification Registers
10.22. Peripheral ID Register 0 bit assignments
10.23. Peripheral ID Register 1 bit assignments
10.24. Peripheral ID Register 2 bit assignments
10.25. Peripheral ID Register 3 bit assignments
10.26. Peripheral ID Register 4 bit assignments
10.27. Component Identification Registers
A.1. Clock and reset signals
A.2. Interrupt signals
A.3. Configuration signals
A.4. Standby and wait for event signals
A.5. Power management signals
A.6. AXI write address channel signals
A.7. AXI write data channel signals
A.8. AXI write data response channel signals
A.9. AXI read address channel signals
A.10. AXI read data signals
A.11. AXI clock enable signal
A.12. Performance monitoring signals
A.13. MBIST interface signals
A.14. Scan test signals
A.15. Authentication interface signals
A.16. APB interface signals
A.17. CTI signals
A.18. Miscellaneous debug signals
A.19. Trace interface signals
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences betwwen issue B and issue C

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A24 December 2009First release for r0p0
Revision B30 September 2010First release for r0p1
Revision C04 January 2016Second release for r0p1
Copyright © 2009, 2010, 2016 ARM. All rights reserved.ARM DDI 0433C