| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0434B |
| Non-Confidential | ID101810 |
 PDF version | |
| Home > Snoop Control Unit > About the SCU |
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The SCU connects between one and four cores in a Cortex-A5 MPCore processor to the memory system. The SCU programmers model also includes support for data security using the TrustZone memory model.
The SCU functions are to:
maintain data cache coherency between the cores
initiate L2 AXI memory accesses
arbitrate between cores requesting L2 accesses
manage Accelerator Coherency Port (ACP) accesses.
The SCU is described in:
| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0434B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > Snoop Control Unit > About the SCU |