9.5. Global timer registers

Addresses are relative to the base address of the timer and watchdog region defined by the SCU memory map, which is determined by PERIPHBASE[31:13].

Access to the global timer registers in Secure and Non-secure state is controlled by the SSAC Register. See SCU Secure Access Control Register.

Table 9.14 shows the global timer registers. All registers not described in Table 9.14 are Reserved. Use nPERIPHRESET to reset these registers.

Table 9.14. Global timer registers

OffsetTypeReset valueDescription

0x200

RW0x00000000Global Timer Counter Registers, 0x00 and 0x04

0x204

RW0x00000000

0x208

RW0x00000000Global Timer Control Register

0x20C

RW

0x00000000

Global Timer Interrupt Status Register

0x210

RW

0x00000000

Comparator Value Registers

0x214

RW

0x00000000

0x218

RW

0x00000000

Auto-increment Register

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