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Addresses are relative to the base address of the timer and watchdog region defined by the SCU memory map, which is determined by PERIPHBASE[31:13].
Access to the global timer registers in Secure and Non-secure state is controlled by the SSAC Register. See SCU Secure Access Control Register.
Table 9.14 shows the global timer registers. All registers not described in Table 9.14 are Reserved. Use nPERIPHRESET to reset these registers.
Table 9.14. Global timer registers
| Offset | Type | Reset value | Description |
|---|---|---|---|
| RW | 0x00000000 | Global Timer Counter Registers, 0x00 and 0x04 |
| RW | 0x00000000 | |
| RW | 0x00000000 | Global Timer Control Register |
| RW |
| Global Timer Interrupt Status Register |
| RW |
| Comparator Value Registers |
| RW |
| |
| RW |
| Auto-increment Register |