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| Non-Confidential | ID101810 |
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In Table 8.2 and Table 8.3, x represents 0 (primary master port) or 1 (secondary master port).
Table 8.2 shows the bit encodings for ARUSERMx[4:0]
Table 8.2. ARUSERMx[4:0] encodings
| Bits | Name | Description |
|---|---|---|
| [4:0] | Inner attributes | b00001 = Strongly ordered b00010 = Device, non-shareable b00011 = Device, shareable b00110 = Non-cacheable, non-shareable b00111 = Non-cacheable, shareable b11110 = Writeback cacheable, read and write allocate, non-shareable b11111 = Writeback cacheable, read and write allocate, shareable |
Table 8.3 shows the bit encodings for AWUSERMx[6:0].
Table 8.3. AWUSERMx[6:0] encodings
| Bits | Name | Description |
|---|---|---|
| [6:5] | Exclusive mode | b00 = Not an eviction b01 = An eviction with dirty data b10 = Not used b11 = An eviction but the data is clean |
| [4:0] | Inner attributes | b00001 = Strongly ordered b00010 = Device, non-shareable b00011 = Device, shareable b00110 = Non-cacheable, non-shareable b00111 = Non-cacheable, shareable b11110 = Writeback cacheable, read and write allocate, non-shareable b11111 = Writeback cacheable, read and write allocate, shareable |
Table 8.2 and Table 8.3 show the attributes after they have been modified by the TLB remapping, and therefore represent the attributes used by the L1 cache, not necessarily the attributes that were stored in the page tables. If the L1 data cache is disabled, all cacheable memory is remapped to non-cacheable.
The ACP interface AXI user bits ARUSERS[4:0] and AWUSERS[4:0] are passed through to the AXI master interfaces. For ACP write requests the corresponding value on AWUSERMx[6:5] is b00. ARUSERS[0] and AWUSERS[0] are used to indicated coherent transactions on ACP.
| Copyright © 2010 ARM. All rights reserved. | ARM DDI 0434B |
| Non-Confidential | ID101810 |
| PDF version | |
| Home > Level 2 Memory Interface > About the L2 interface > AXI user bits |