Cortex-A5 MPCore Technical Reference ManualRevision: r0p1
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4.3.26. Auxiliary Control Register

The ACTLR characteristics are:

Purpose

Controls extended processor functionality from software, such as:

  • behavior of the direct and indirect branch prediction in the Prefetch Unit (PFU)

  • the limited dual issue capability of the Data Processing Unit (DPU)

  • coherency mode, Symmetric Multiprocessing (SMP) or Asymmetric Multiprocessing (AMP).

Usage constraints

The ACTLR is:

  • Only accessible in privileged modes.

  • Common to the Secure and Non-secure states.

  • RW in Secure state

  • RO in Non-secure state if NSACR.NS_SMP=0

  • RW in Non-secure state if NSACR.NS_SMP=1. In this case all bits are Write Ignore except for the SMP bit.

Attempts to write to this register in Secure privileged mode when CP15SDISABLE is HIGH result in an Undefined instruction exception, see Security Extensions write access disable.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.10.

Figure 4.26 shows the ACTLR bit assignments.

Figure 4.26. ACTLR bit assignments

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Table 4.44 shows the ACTLR bit assignments.

Table 4.44. ACTLR bit assignments

BitsNameDescription
[31:29]ReservedRAZ/WI.
[28]DBDIDisable branch dual issue.
[27:19]ReservedRAZ/WI.
[18]BTDISDisable indirect Branch Target Address Cache (BTAC).
[17]RSDISDisable return stack operation.
[16:15]BP

Branch prediction policy:

00 = Normal operation

01 = Branch always taken

10 = Branch always not taken

11 = Reserved (Unpredictable).

[14:13]L1PCTL

L1 Data prefetch control. The value of this field determines the maximum number of outstanding data prefetches allowed in the L1 memory system, not counting those generated by software load/PLD instructions:

00 = prefetch disabled

01 = 1 outstanding prefetch allowed

10 = 2 outstanding prefetches allowed

11 = 3 outstanding prefetches allowed.

[12]RADISDisable Data Cache read-allocate mode. See Read allocate mode.
[11]DWBSTDisable data write bursts to normal non-cacheable memory. Set in conjunction with RADIS to disable data write bursts to cacheable memory..
[10]DODMBSDisable optimized Data Memory Barrier behavior.
[9:8]ReservedRAZ/WI.
[7]EXCL[a]

Exclusive L1/L2 cache control.

The exclusive cache configuration does not permit data to reside in the L1 and L2 caches at the same time. The exclusive cache configuration provides support for only caching data on an eviction from L1 when the inner cache attributes are Write-Back, Cacheable and allocated in L1. For this feature to operate correctly, the L2 cache controller must also be configured for exclusive caching.

[6]SMP

Enable data coherency with other cores in the Cortex-A5 MPCore processor. When this bit is reset, data requests with Inner Cacheable shared attributes are treated as Non-cacheable.

0 = disabled.

1 = enabled.

[5:1]ReservedRAZ/WI.
[0]FW

Cache and TLB maintenance broadcast:

0 = disabled.

1 = enabled.

The SMP bit must also be set in the ACTLR for Cache and TLB maintenance operations to be broadcast by the core and received from other cores in the Cortex-A5 MPCore processor.

[a] This feature must only be enabled when the Cortex-A5 MPCore processor AXI master interface is directly connected to a PL310 L2 cache controller.


To access the ACTLR you must use a read modify write technique. To access the ACTLR, use:

MRC p15, 0, <Rd>, c1, c0, 1 ; Read ACTLR

MCR p15, 0, <Rd>, c1, c0, 1 ; Write ACTLR
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