The remap capability falls into two levels, the primary remap, enables the primary memory type (Normal, Device, or Strongly-ordered) to be remapped. For Device and Normal memory, the effect of the S bit can be independently remapped. To provide maximum flexibility, this level of remapping enables regions that were originally not Normal memory to be remapped independently. The remapping is applied to all sources of TLB requests.

After this primary remapping is performed any region that is mapped as Normal memory can have the inner and outer cacheable attributes determined by the Normal Memory Remap Register (NMRR).

The memory region remap registers are accessed by:

MCR/MRC p15, 0, Rd, c10, c2, 0;access primary memory region remap register

MCR/MRC p15, 0, Rd, c10, c2, 1;access normal memory region remap register

These registers are used to remap memory region types. This remapping is enabled when the TRE bit of the System Control Register (SCTLR) is set. The remapping takes place on the page table values, and overrides the settings specified in the page tables. The remapping does not take place when the MMU is turned off.

Table 4.6 and Table 4.7 show the encoding used for each memory type.

Table 4.6 shows the primary remapping encodings.

Table 4.7 shows the normal remapping encodings.