Cortex-A5™ MPCore™ Technical Reference Manual

Revision: r0p1

Table of Contents

About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback on this product
Feedback on content
1. Introduction
1.1. About the Cortex-A5 MPCore processor
1.1.1. Floating-Point Unit
1.1.2. Media Processing Engine
1.1.3. System design components
1.2. Variants
1.3. Compliance
1.4. Features
1.5. Interfaces
1.6. Configurable options
1.7. Test features
1.8. Product documentation, design flow, and architecture
1.8.1. Documentation
1.8.2. Design flow
1.8.3. Architecture and protocol information
1.9. Product revisions
2. Functional Description
2.1. About the functions
2.1.1. Data Processing Unit
2.1.2. System control coprocessor
2.1.3. Instruction side memory system
2.1.4. Data side memory system
2.1.5. L1 memory system
2.1.6. Media Processing Engine
2.1.7. Floating-Point Unit
2.1.8. Snoop Control Unit
2.1.9. Debug
2.1.10. Performance monitoring
2.1.11. Virtualization extensions
2.2. Interfaces
2.2.1. ETM interface
2.3. Clocking and resets
2.3.1. Clocking
2.3.2. Resets
2.4. Power management
2.4.1. Individual Cortex-A5 core power management
2.4.2. Power domains
2.4.3. Communication to the Power Management Controller
2.4.4. IEM support
2.5. Multiprocessor bring-up
3. Programmers Model
3.1. About the programmers model
3.2. Jazelle extension
3.3. NEON technology
3.4. Processor operating states
3.4.1. Switching state
3.4.2. Interworking ARM and Thumb code sequences
3.5. Data types
3.6. Memory formats
3.7. Addresses in the Cortex-A5 MPCore processor
3.8. Security Extensions overview
3.8.1. System boot sequence
3.8.2. Security Extensions write access disable
4. System Control
4.1. About system control
4.1.1. System control functional groups
4.1.2. System control and configuration
4.1.3. MMU control and configuration
4.1.4. Cache control and configuration
4.1.5. Cache Operations Registers
4.1.6. System performance monitor registers
4.1.7. System feature registers
4.1.8. c0, Instruction set attributes registers
4.1.9. c7, VA to PA operations
4.1.10. c8, TLB maintenance operations
4.1.11. c10, Memory region remap
4.1.12. c13, Software Thread ID Registers
4.1.13. c15, TLB access and attributes
4.2. Register summary
4.2.1. Virtualization
4.2.2. c0 summary table
4.2.3. c1 summary table
4.2.4. c2 summary table
4.2.5. c3 summary table
4.2.6. c4 summary table
4.2.7. c5 summary table
4.2.8. c6 summary table
4.2.9. c7 summary table
4.2.10. c8 summary table
4.2.11. c9 summary table
4.2.12. c10 summary table
4.2.13. c11 summary table
4.2.14. c12 summary table
4.2.15. c13 summary table
4.2.16. c14 summary table
4.2.17. c15 summary table
4.3. Register descriptions
4.3.1. Main ID Register
4.3.2. Cache Type Register
4.3.3. TCM Type Register
4.3.4. TLB Type Register
4.3.5. Multiprocessor Affinity Register
4.3.6. Processor Feature Register 0
4.3.7. Processor Feature Register 1
4.3.8. Debug Feature Register 0
4.3.9. Auxiliary Feature Register 0
4.3.10. Memory Model Features Register 0
4.3.11. Memory Model Features Register 1
4.3.12. Memory Model Features Register 2
4.3.13. Memory Model Features Register 3
4.3.14. Instruction Set Attributes Register 0
4.3.15. Instruction Set Attributes Register 1
4.3.16. Instruction Set Attributes Register 2
4.3.17. Instruction Set Attributes Register 3
4.3.18. Instruction Set Attributes Register 4
4.3.19. Instruction Set Attributes Register 5
4.3.20. Instruction Set Attributes Registers 6-7
4.3.21. Cache Size Identification Register
4.3.22. Cache Level ID Register
4.3.23. Auxiliary ID Register
4.3.24. Cache Size Selection Register
4.3.25. System Control Register
4.3.26. Auxiliary Control Register
4.3.27. Coprocessor Access Control Register
4.3.28. Secure Configuration Register
4.3.29. Secure Debug Enable Register
4.3.30. Non-secure Access Control Register
4.3.31. Virtualization Control Register
4.3.32. Translation Table Base Register 0
4.3.33. Translation Table Base Register 1
4.3.34. Translation Table Base Control Register
4.3.35. Domain Access Control Register
4.3.36. Data Fault Status Register
4.3.37. Instruction Fault Status Register
4.3.38. Auxiliary Data Fault Status Register
4.3.39. Auxiliary Instruction Fault Status Register
4.3.40. Data Fault Address Register
4.3.41. Instruction Fault Address Register
4.3.42. NOP Register
4.3.43. Physical Address Register
4.3.44. Instruction Synchronization Barrier
4.3.45. Data Synchronization Barrier
4.3.46. Data Memory Barrier
4.3.47. Vector Base Address Register
4.3.48. Monitor Vector Base Address Register
4.3.49. Interrupt Status Register
4.3.50. Virtualization Interrupt Register
4.3.51. Context ID Register
4.3.52. Configuration Base Address Register
5. Non-debug Use of CP14
5.1. About coprocessor CP14
5.2. CP14 Jazelle register summary
5.3. CP14 Jazelle register descriptions
5.3.1. Jazelle Identity and Miscellaneous Functions Register
5.3.2. Jazelle Operating System Control Register
5.3.3. Jazelle Main Configuration Register
5.3.4. Jazelle Parameters Register
5.3.5. Jazelle Configurable Opcode Translation Table Register
6. Memory Management Unit
6.1. About the MMU
6.2. Memory management system
6.2.1. Memory types
6.3. TLB organization
6.3.1. Micro TLB
6.3.2. Main TLB
6.4. Memory access sequence
6.5. Interaction with memory system
6.6. External aborts
6.6.1. External aborts on data write
6.6.2. Synchronous and asynchronous aborts
6.7. MMU software accessible registers
7. Level 1 Memory System
7.1. About the L1 memory system
7.1.1. Memory system
7.2. Security extensions support
7.3. L1 instruction side memory system
7.3.1. Enabling program flow prediction
7.3.2. Program flow prediction
7.4. L1 data side memory system
7.4.1. Internal exclusive monitor
7.4.2. External aborts handling
7.5. Data prefetching
7.5.1. The PLD instruction
7.5.2. Data prefetching and monitoring
7.6. Direct access to internal memory
7.6.1. Data Cache Tag and Data encoding
7.6.2. Instruction Cache Tag and Data encoding
7.6.3. TLB data encoding
8. Level 2 Memory Interface
8.1. About the L2 interface
8.1.1. AXI master interface
8.1.2. L2 memory interface attributes
8.1.3. Supported AXI transfers
8.1.4. AXI transaction IDs
8.1.5. AXI user bits
8.1.6. Write response
8.1.7. Exclusive L2 cache
8.2. AXI privilege information
9. Snoop Control Unit
9.1. About the SCU
9.1.1. Cache coherency
9.1.2. SCU master interface
9.1.3. Accelerator Coherency Port
9.1.4. Timer and watchdog
9.1.5. Global timer
9.2. Cortex-A5 MPCore configuration and control registers
9.3. SCU registers
9.3.1. SCU Control Register
9.3.2. SCU Configuration Register
9.3.3. SCU CPU Power Status Register
9.3.4. SCU Invalidate All in Secure State Register
9.3.5. SCU Filtering Start Address Register
9.3.6. SCU Filtering End Address Register
9.3.7. SCU Access Control Register
9.3.8. SCU Secure Access Control Register
9.4. Timer and watchdog registers
9.4.1. Timer Load Register
9.4.2. Timer Counter Register
9.4.3. Timer Control Register
9.4.4. Timer Interrupt Status Register
9.4.5. Watchdog Load Register
9.4.6. Watchdog Counter Register
9.4.7. Watchdog Control Register
9.4.8. Watchdog Interrupt Status Register
9.4.9. Watchdog Reset Status Register
9.4.10. Watchdog Disable Register
9.5. Global timer registers
9.5.1. Global Timer Counter Registers, 0x00 and 0x04
9.5.2. Global Timer Control Register
9.5.3. Global Timer Interrupt Status Register
9.5.4. Comparator Value Registers
9.5.5. Auto-increment Register
10. Interrupt Controller
10.1. About the interrupt controller
10.1.1. Interrupt Controller clock frequency
10.1.2. Interrupt types and sources
10.1.3. TrustZone support
10.2. Interrupt distributor registers
10.2.1. Distributor Control Register
10.2.2. Interrupt Controller Type Register
10.2.3. Distributor Implementer Identification Register
10.2.4. Private Peripheral Interrupt Status Register
10.2.5. Shared Peripheral Interrupt Status Registers
10.2.6. Peripheral Identification Registers
10.2.7. Component Identification Registers
10.3. Processor interface registers
10.3.1. Processor Interface Implementer Identification Register
11. Debug
11.1. About debug
11.1.1. Debug host
11.1.2. Protocol converter
11.1.3. Debug target
11.1.4. About the debug unit
11.1.5. Debug configuration
11.2. Debugging modes
11.2.1. Halting debug-mode debugging
11.2.2. Monitor debug-mode debugging
11.2.3. Performance monitor and events
11.2.4. Security extensions and debugging
11.3. Debug interface
11.3.1. Breakpoints and watchpoints
11.3.2. Asynchronous aborts
11.3.3. Processor interfaces
11.3.4. Effects of resets on debug registers
11.4. Debug register summary
11.5. Debug register descriptions
11.5.1. Debug Identification Register
11.5.2. Debug Status and Control Register
11.5.3. Program Counter Sampling Register
11.5.4. Debug State Cache Control Register
11.5.5. Event Catch Register
11.5.6. Debug State MMU Control Register
11.5.7. Operating System Lock and Save/Restore Registers
11.5.8. Debug Run Control Register
11.5.9. Breakpoint Value Registers
11.5.10. Breakpoint Control Registers
11.5.11. Watchpoint Value Register
11.5.12. Watchpoint Control Register
11.5.13. Device Power-down and Reset Control Register
11.5.14. Device Power-down and Reset Status Register
11.6. Management registers
11.6.1. Processor ID Registers
11.6.2. Claim Tag Set Register
11.6.3. Claim Tag Clear Register
11.6.4. Lock Access Register
11.6.5. Lock Status Register
11.6.6. Authentication Status Register
11.6.7. Device Type Register
11.6.8. Identification Registers
11.7. Integration test registers
11.7.1. Processor integration testing
11.8. External debug interface
11.9. Miscellaneous debug signals
11.9.1. EDBGRQ
11.9.2. DBGACK
11.9.3. COMMRX and COMMTX
11.9.4. Memory mapped accesses, DBGROMADDR, and DBGSELFADDR
11.9.5. Authentication signals
11.9.6. Changing the authentication signals
12. Performance Monitoring Unit
12.1. About the Performance Monitoring Unit
12.2. Performance monitoring register descriptions
12.2.1. Performance Monitor Control Register
12.2.2. Count Enable Set Register
12.2.3. Count Enable Clear Register
12.2.4. Overflow Flag Status Register
12.2.5. Software Increment Register
12.2.6. Event Counter Selection Register
12.2.7. Common Event Identification Registers
12.2.8. Cycle Count Register
12.2.9. Event Type Select Register
12.2.10. Cycle Count Filter Control Register
12.2.11. Event Count Registers
12.2.12. User Enable Register
12.2.13. Interrupt Enable Set Register
12.2.14. Interrupt Enable Clear Register
12.2.15. Configuration Register
12.2.16. Lock Access Register
12.2.17. Lock Status Register
12.2.18. Authentication Status Register
12.2.19. Device Type Register
12.2.20. Identification Registers
A. Signal Descriptions
A.1. Signal descriptions
A.1.1. Clock and reset signals
A.1.2. Interrupt signals
A.1.3. Configuration signals
A.1.4. Standby and wait for event signals
A.1.5. Power management signals
A.1.6. AXI master interfaces
A.1.7. ACP interface
A.1.8. Performance monitoring signals
A.1.9. MBIST interface
A.1.10. Scan test signals
A.1.11. External debug interface
A.1.12. Trace interface signals
B. Revisions

List of Figures

1. Key to timing diagram conventions
2.1. Example Cortex-A5 MPcore configuration
2.2. Cortex-A5 CPU core top-level diagram
2.3. ETM interface signals
2.4. Trace architecture
2.5. Clocking example on Cortex-A5 MPCore peripherals
2.6. AXI master port clocking at a ratio of 3:1 using ACLKENM0
2.7. Power domains
4.1. Set/Way bit assignments
4.2. CP15 Register c7 VA bit assignments
4.3. VA to PA register bit assignments
4.4. TLB Operations Register Virtual Address bit assignments
4.5. TLB Operations Register ASID bit assignments
4.6. Thread ID register bit assignments
4.7. MIDR bit assignments
4.8. CTR bit assignments
4.9. MPIDR bit assignments
4.10. ID_PFR0 bit assignments
4.11. ID_PFR1 bit assignments
4.12. ID_DFR0 bit assignments
4.13. ID_MMFR0 bit assignments
4.14. ID_MMFR1 bit assignments
4.15. ID_MMFR2 bit assignments
4.16. ID_MMFR3 bit assignments
4.17. ID_ISAR0 bit assignments
4.18. ID_ISAR1 bit assignments
4.19. ID_ISAR2 bit assignments
4.20. ID_ISAR3 bit assignments
4.21. ID_ISAR4 bit assignments
4.22. CCSIDR bit assignments
4.23. CLIDR bit assignments
4.24. CSSELR bit assignments
4.25. SCTLR bit assignments
4.26. ACTLR bit assignments
4.27. CPACR bit assignments
4.28. SCR bit assignments
4.29. SDER bit assignments
4.30. NSACR bit assignments
4.31. VCR bit assignments
4.32. TTBR0 bit assignments
4.33. TTBR1 bit assignments
4.34. TTBCR bit assignments
4.35. DACR bit assignments
4.36. DFSR bit assignments
4.37. IFSR bit assignments
4.38. PAR aborted translation bit assignments
4.39. PAR successful translation bit assignments
4.40. VBAR bit assignments
4.41. MVBAR bit assignments
4.42. ISR bit assignments
4.43. VIR bit assignments
4.44. CONTEXTIDR bit assignments
4.45. CBAR bit assignments
5.1. JIDR bit assignment
5.2. JOSCR bit assignments
5.3. JMCR bit assignments
5.4. JPR bit assignments
5.5. JCOTTR bit assignments
9.1. SCU Control Register bit assignments
9.2. SCU Configuration Register bit assignments
9.3. SCU CPU Power Status Register bit assignments
9.4. SCU Invalidate All in Secure State Register bit assignments
9.5. SCU Filtering Start Address Register bit assignments
9.6. SCU Filtering End Address Register bit assignments
9.7. SAC Register bit assignments
9.8. SSAC Register bit assignments
9.9. Timer Control Register bit assignments
9.10. Timer Interrupt Status Register bit assignments
9.11. Watchdog Control Register bit assignments
9.12. Watchdog Interrupt Status Register bit assignments
9.13. Watchdog Reset Status Register bit assignments
9.14. Global Timer Control Register bit assignments
9.15. Global Timer Interrupt Status Register bit assignments
10.1. ICDDCR bit assignments for Secure accesses
10.2. ICDDCR bit assignments for Non-secure accesses
10.3. ICDICTR bit assignments
10.4. ICDIIDR bit assignments
10.5. ICDPPIS Register bit assignments
10.6. ICDSPIS Register bit assignments
10.7. ICDSPIS Register address map
10.8. Peripheral ID [3:0] Register bit assignments
10.9. Peripheral ID [7:4] Register bit assignments
10.10. Component ID Register bit assignments
10.11. ICCIIDR bit assignments
11.1. Typical debug system
11.2. Cortex-A5 MPCore debug configuration including cross trigger support
11.3. DBGDIDR bit assignments
11.4. DBGDSCR bit assignments
11.5. DBGPCSR bit assignments
11.6. DBGDRCR bit assignments
11.7. DBGBCR bit assignments
11.8. DBGWCR bit assignments
11.9. DBGPRCR bit assignments
11.10. DBGPRSR bit assignments
11.11. DBGCLAIMSET Register bit assignments
11.12. DBGCLAIMCLR Register bit assignments
11.13. DBGLAR Register bit assignments
11.14. DBGLSR Register bit assignments
11.15. DBGAUTHSTATUS Register bit assignments
11.16. DBGDEVTYPE Register bit assignments
11.17. DBGITMISCOUT Register bit assignments
11.18. DBGITMISCIN Register bit assignments
11.19. DBGITCTRL Register bit assignments
11.20. External debug interface signals
12.1. PMCR bit assignments
12.2. PMCNTENSET Register bit assignments
12.3. PMCNTENCLR Register bit assignments
12.4. PMSOVSR bit assignments
12.5. PMSWINC Register bit assignments
12.6. PMSELR bit assignments
12.7. PMXEVTYPER bit assignments
12.8. PMCCFILTR bit assignments
12.9. PMUSERENR bit assignments
12.10. PMINTENSET Register bit assignments
12.11. PMINTENCLR Register bit assignments
12.12. PMCFGR bit assignments
12.13. PMLAR bit assignments
12.14. PMLSR bit assignments
12.15. PMAUTHSTATUS Register bit assignments
12.16. PMDEVTYPE Register bit assignments

List of Tables

1.1. Configurable options for the Cortex-A5 MPCore
2.1. Supported power configurations
2.2. Cortex-A5 MPCore power control signal encoding
3.1. CPSR J and T bit encoding
4.1. System registers affected by CP15SDISABLE
4.2. Cache operation functions
4.3. Set/Way bit assignments
4.4. Cache size and S parameter dependency
4.5. TLB Operations Register instructions
4.6. Primary remapping encodings
4.7. Inner or outer region type encodings
4.8. TLBHR data format
4.9. c0 system control registers
4.10. c1 system control registers
4.11. c2 system control registers
4.12. c3 system control register
4.13. c5 system control registers
4.14. c6 system control registers
4.15. c7 system control registers
4.16. c8 system control register
4.17. c9 system control registers
4.18. c10 system control registers
4.19. c12 system control registers
4.20. c13 system control registers
4.21. c15 system control registers
4.22. MIDR bit assignments
4.23. CTR bit assignments
4.24. MPIDR bit assignments
4.25. ID_PFR0 bit assignments
4.26. ID_PFR1 bit assignments
4.27. ID_DFR0 bit assignments
4.28. ID_AFR0 bit assignments
4.29. ID_MMFR0 bit assignments
4.30. ID_MMFR1 bit assignments
4.31. ID_MMFR2 bit assignments
4.32. ID_MMFR3 bit assignments
4.33. ID_ISAR0 bit assignments
4.34. ID_ISAR1 bit assignments
4.35. ID_ISAR2 bit assignments
4.36. ID_ISAR3 bit assignments
4.37. ID_ISAR4 bit assignments
4.38. ID_ISAR5 bit assignments
4.39. CCSIDR bit assignments
4.40. CLIDR bit assignments
4.41. AIDR bit assignments
4.42. CSSELR bit assignments
4.43. SCTLR bit assignments
4.44. ACTLR bit assignments
4.45. CPACR bit assignments
4.46. Results of access to the CPACR
4.47. SCR bit assignments
4.48. Operation of the SCR FW and FIQ bits
4.49. Operation of the SCR AW and EA bits
4.50. SDER bit assignments
4.51. NSACR bit assignments
4.52. Results of access to the NSACR
4.53. VCR bit assignments
4.54. TTBR0 bit assignments
4.55. TTBR1 bit assignments
4.56. TTBCR bit assignments
4.57. DACR bit assignments
4.58. DFSR bit assignments
4.59. IFSR bit assignments
4.60. PAR bit assignments
4.61. VBAR bit assignments
4.62. MVBAR bit assignments
4.63. ISR bit assignments
4.64. VIR bit assignments
4.65. CONTEXTIDR bit assignments
5.1. CP14 Jazelle registers summary
5.2. JIDR bit assignments
5.3. JOSCR bit assignments
5.4. JMCR bit assignments
5.5. Jazelle Parameters Register bit assignments
5.6. JCOTTR bit assignments
6.1. Treatment of memory attributes
6.2. CP15 register functions
7.1. Cortex-A5 MPCore system coprocessor CP15 registers used to access internal memory
7.2. Data Cache Tag and Data location encoding
7.3. Data Cache Tag data format
7.4. Instruction Cache Tag and Data location encoding
7.5. Instruction Cache Tag data format
7.6. TLB Data Read Operation Register location encoding
7.7. TLB descriptor format
8.1. AXI master interface attributes
8.2. ARUSERMx[4:0] encodings
8.3. AWUSERMx[6:0] encodings
8.4. Cortex-A5 MPCore mode and APROT values
9.1. Cortex-A5 memory-mapped registers
9.2. SCU register summary
9.3. SCU Control Register bit assignments
9.4. SCU Configuration Register bit assignments
9.5. SCU CPU Power Status Register bit assignments
9.6. SCU Invalidate All in Secure State Register bit assignments
9.7. SCU Filtering Start Address Register bit assignments
9.8. SCU Filtering End Address Register bit assignments
9.9. SAC Register bit assignments
9.10. SSAC Register bit assignments
9.11. Timer and watchdog registers 
9.12. Timer Control Register bit assignments 
9.13. Watchdog Control Register bit assignments 
9.14. Global timer registers
9.15. Global Timer Control Register bit assignments 
10.1. Distributor register summary
10.2. ICDDCR bit assignments for secure accesses
10.3. ICDDCR bit assignments for Non-secure accesses
10.4. ICDICTR bit assignments
10.5. ICDIIDR bit assignments
10.6. ICDPPIS Register bit assignments
10.7. ICDSPIS Register bit assignments
10.8. Peripheral ID [3:0] Register bit assignments
10.9. Peripheral ID 0 Register bit assignments
10.10. Peripheral ID 1 Register bit assignments
10.11. Peripheral ID 2 Register bit assignments
10.12. Peripheral ID 3 Register bit assignments
10.13. Peripheral ID [7:4] Register bit assignments
10.14. Peripheral ID 4 Register bit assignments
10.15. Component ID Register bit assignments
10.16. Component ID 0 Register bit assignments
10.17. Component ID 1 Register bit assignments
10.18. Component ID 2 Register bit assignments
10.19. Component ID 3 Register bit assignments
10.20. Cortex-A5 MPCore processor interface register summary
10.21. ICCIIDR bit assignments
11.1. Debug interface registers
11.2. DBGDIDR bit assignments
11.3. DBGDSCR bit assignments
11.4. DBGPCSR bit assignments
11.5. DBGDRCR bit assignments
11.6. DBGBVRs and corresponding DBGBCRs
11.7. DBGBVR bit assignments
11.8. DBGBCR bit assignments
11.9. Meaning of DBGBVR bits [22:20]
11.10. DBGWVR and corresponding DBGWCR
11.11. DBGWVR bit assignments
11.12. DBGWCR bit assignments
11.13. DBGPRCR bit assignments
11.14. DBGPRSR bit assignments
11.15. Management registers
11.16. Processor Identifier Registers
11.17. DBGCLAIMSET Register bit assignments
11.18. DBGCLAIMCLR Register bit assignments
11.19. DBGLAR Register bit assignments
11.20. DBGLSR Register bit assignments
11.21. DBGAUTHSTATUS Register bit assignments
11.22. DBGDEVTYPE Register bit assignments
11.23. Peripheral Identification Registers
11.24. Peripheral ID Register 0 bit assignments
11.25. Peripheral ID Register 1 bit assignments
11.26. Peripheral ID Register 2 bit assignments
11.27. Peripheral ID Register 3 bit assignments
11.28. Peripheral ID Register 4 bit assignments
11.29. Component Identification Registers
11.30. Output signals that can be controlled by the Integration Test Registers
11.31. Input signals that can be read by the Integration Test Registers
11.32. DBGITMISCOUT Register bit assignments
11.33. DBGITMISCIN Register bit assignments
11.34. DBGITCTRL Register bit assignments
11.35. Address mapping used to access the debug interface for a core in the Cortex-A5 MPCore processor
11.36. Authentication signal restrictions
12.1. Performance monitoring instructions and APB mapping
12.2. PMCR bit assignments
12.3. PMCNTENSET Register bit assignments
12.4. PMCNTENCLR Register bit assignments
12.5. PMSOVSR Register bit assignments
12.6. PMSWINC Register bit assignments
12.7. PMSELR bit assignments
12.8. PMCEID0 Register bit assignments
12.9. PMXEVTYPER bit assignments
12.10. Performance monitor events
12.11. PMCCFILTR bit assignments
12.12. Signal settings for the PMXEVCNTR
12.13. PMUSERENR bit assignments
12.14. PMINTENSET Register bit assignments
12.15. PMINTENCLR Register bit assignments
12.16. PMCFGR bit assignments
12.17. PMLAR bit assignments
12.18. PMLSR bit assignments
12.19. PMAUTHSTATUS Register bit assignments
12.20. PMDEVTYPE Register bit assignments
12.21. Peripheral Identification Registers
12.22. Peripheral ID Register 0 bit assignments
12.23. Peripheral ID Register 1 bit assignments
12.24. Peripheral ID Register 2 bit assignments
12.25. Peripheral ID Register 3 bit assignments
12.26. Peripheral ID Register 4 bit assignments
12.27. Component Identification Registers
A.1. Clock and reset signals
A.2. Interrupt signals
A.3. Configuration signals
A.4. Standby and wait for event signals
A.5. Power management signals
A.6. AXI master write address channel signals
A.7. AXI master write data channel signals
A.8. AXI master write data response channel signals
A.9. AXI master read address channel signals
A.10. AXI master read data signals
A.11. AXI master clock enable signals
A.12. AXI slave write address channel signals
A.13. AXI slave write data channel signals
A.14. AXI slave write data response channel signals
A.15. AXI slave read address channel signals
A.16. AXI slave read data signals
A.17. AXI slave clock enable signal
A.18. Performance monitoring signals
A.19. MBIST interface signals
A.20. Scan test signals
A.21. Authentication interface signals
A.22. APB interface signals
A.23. CTI signals
A.24. Miscellaneous debug signals
A.25. Trace interface signals
B.1. Issue A
B.2. Differences between issue A and issue B
B.3. Differences betwwen issue B and issue C

Proprietary Notice

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Revision History
Revision A28 May 2010First release for r0p0
Revision B30 September 2010First release for r0p1
Revision C04 January 2016Second release for r0p1
Copyright © 2010, 2016 ARM. All rights reserved.ARM DDI 0434C