A.1. Signal descriptions

Table A.1 shows the ETM-A5 signals in alphabetical order. All input signals are sampled and output signals generated on one of three clocks CLK, ATCLK, or PCLKDBG. ATCLK and PCLKDBG must either be the same clock as CLK, or synchronously divided versions of CLK, using the ATCLKEN and PCLKENDBG enable signals. See the CoreSight ETM-A5 Integration Manual for information about signals and connectivity.

Table A.1. ETM-A5 signals

SignalTypeClockDescription
AFREADYOutputATCLKATB interface FIFO flush finished.
AFVALIDInputATCLKATB interface FIFO flush request.
ASICCTL[7:0]OutputCLKContents of ASICCTL Register.
ATBYTES[1:0]OutputATCLKSize of ATDATA.
ATCLKENInputCLKClock enable for ATB interface.
ATDATA[31:0]OutputATCLKATB interface data.
ATID[6:0]OutputATCLKATB interface trace source ID.
ATREADYInputATCLKATDATA can be accepted.
ATVALIDOutputATCLKATB interface data valid.
CLKInputn/aETM clock. Same as Cortex-A5 processor clock.
CLKCHANGEInputCLKClock change indicator input. It is used when either the processor clock period or timestamp period changes.
CORESELECT[2:0]OutputCLK

Where an ETM is shared between multiple cores, this signal specifies which core to trace.

The value appears as bits [14:12] of the System Configuration Register.

DBGACKInputCLK

Indicates that the core is in debug state.

This signal is connected to the core general purpose DBGACK output, so that it can be used to determine when ETMDBGRQ can be deasserted. It is also used for other purposes in the ETM, and care must be taken to ensure the timing of this signal is appropriate because it does not come through the main interface between the core and the ETM.

DBGENInputCLK

Invasive debug enable.

When HIGH (1), indicates that invasive debug is enabled.

ETMCID[31:0]InputCLK

Current value of the processor Context ID Register.

ETMDA[31:0]InputCLKAddress for data transfer.
ETMDBGRQOutputCLKRequest from the macrocell for the core to enter debug state. This must be ORed with any ASIC-level DBGRQ signals before being connected to the core EDBGRQ input.
ETMDCTL[10:0]InputCLKData control signals.
ETMDD[31:0]InputCLKContains the data value for a Load, Store, MRC, or MCR instruction.
ETMENOutputCLKEnable signal for trace output from the ETM, driven by bit [11] of the ETMCR.
ETMIA[31:0]InputCLKAddress for executed instruction.
ETMICTL[19:0]InputCLKInstruction control signals.
ETMPWRUPOutputCLK

When HIGH, indicates that the macrocell is in use.

When LOW:

  • external logic supporting the macrocell can be clock-gated to conserve power

  • the Cortex-A5 processor disables the interface

  • logic within the macrocell is clock-gated to conserve power.

ETMSTANDBYWFXOutputCLKIndicates that the macrocell FIFO is empty and that the Cortex-A5 processor can be put into Standby mode.
ETMWFXPENDINGInputCLKIndicates that the Cortex-A5 processor is about to go into Standby mode, and that the ETM must drain its FIFO.
EVNTBUS[29:0]InputCLKGives the status of the performance monitoring events. Used as extended external inputs.
EXTIN[3:0]InputCLKExternal input resources.
EXTOUT[1:0]OutputCLKExternal outputs.
FIFOPEEK[6:0]OutputCLK

For validation purposes only.

Indicates when various events occur before being written to the FIFO.

MAXCORES[2:0]InputCLK

Where an ETM is shared between multiple cores, this signal specifies the number of cores the ETM can trace. It must be tied to the number of cores sharing the ETM minus 1.

These signals determine the value of bits [14:12] of the System Configuration register, see the footnote to Table 3.1.

MAXEXTIN[2:0]InputCLK

Number of external inputs supported by the ASIC (maximum 4).

These signals determine the value bits [19:17] in the ETMCCR, see Configuration Code Register.

MAXEXTOUT[1:0]InputCLK

Number of external outputs supported by the ASIC (maximum 2).

These signals determine the value bits [22:20] in the ETMCCR, see Configuration Code Register.

NIDENInputCLK

Non-invasive debug enable.

When HIGH (1), indicates that non-invasive debug is enabled.

nSYSPORESETInputn/a

Power-on (main) reset.

PADDRDBG[11:2]InputPCLKDBG

Debug APB Address Bus.

PADDRDBG31InputPCLKDBG

Indicates an external debug request from the Debug Access Port (DAP):

  • PADDRDBG31 at logic 1 indicates an access from hardware (JTAG)

  • PADDRDBG31 at logic 0 indicates an access from software.

PCLKENDBGInputCLKDebug APB clock enable.
PENABLEDBGInputPCLKDBGThe Debug APB interface is enabled for a transfer.
PRDATADBG[31:0]OutputPCLKDBGDebug APB read data.
PREADYDBGOutputPCLKDBGUsed to extend Debug APB transfers.
PSELDBGInputPCLKDBGDebug APB slave select signal.
PWDATADBG[31:0]InputPCLKDBGDebug APB write data.
PWRITEDBGInputPCLKDBG

Debug APB transfer direction:

0 = Read

1 = Write.

DFTRSTDISABLEInputCLKReset synchronization bypass DFT signal.
DFTSEInputCLKScan enable DFT signal.
SYNCREQInputATCLKRequest for periodic synchronization.
TRIGGEROutputATCLKTrigger request status signal. Asserted for one clock cycle when a trigger occurs..
TSMAXWIDTHInputCLK

Timestamp maximum size:

0 = 48 bits

1 = 64 bits.

TSNATURALInputCLK

The timestamp is natural binary encoded:

0 = Gray encoded

1 = Binary encoded.

TSVALUE[63:0]InputCLKTimestamp value input bus.

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