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The ETMPDSR characteristics are:
Indicates the power-down status of the ETM.
There are no usage constraints.
Always available.
Figure 3.7 shows the ETMPDSR bit assignments.
Table 3.15 shows the ETMPDSR bit assignments.
Table 3.15. ETMPDSR bit assignments
| Bits | Value | Description |
|---|---|---|
| [31:6] | 0 | Reserved, RAZ |
| [5] | LK | OS lock status. ETM-A5 does not implement the OS lock mechanism, so this bit is RAZ. |
| [4:2] | 0 | Reserved, RAZ |
| [1] | 0 | Sticky Register State. ETM-A5 does not support multiple power domains so this bit is RAZ. |
| [0] | 1 | ETM powered up. The ETM Trace registers are accessible. ETM-A5 does not support multiple power domains so this bit is RAO. |