3.5.4. ETM ID Register

The ETMIDR characteristics are:


Identifies the implementation of the ETM.

Usage constraints

There are no usage constraints.


Always available.


This register has the value 0x410CF25x, where x depends on the release version of the macrocell, see the Implementation revision field description in Table 3.12 for more information.

See the register summary in Table 3.1 and Table 3.3.

Figure 3.4 shows the ETMIDR bit assignments.

Figure 3.4. ETMIDR bit assignments

Table 3.12 shows the ETMIDR bit assignments.

Table 3.12. ETMIDR bit assignments

[31:24]0x41Implementer = A (for ARM).
[20]0Branch packet encoding implemented. This bit is set to 0, indicating that ETM-A5 implements the original branch packet encoding.
[19]1Support for Security Extensions. This bit is set to 1, indicating that the ARM architecture Security Extensions are implemented by the processor.

Support for 32-bit Thumb instructions.

On the macrocell, this bit is set to 1, meaning that all 32-bit Thumb instructions are traced as a single instruction, including BL and BLX immediate.


Load PC first.

On the macrocell, this bit is not set (=0), meaning that on an LSM[a] load operation with the PC included in the load list, the PC is not loaded first.


ARM processor family.

The value of b1111 means that the processor family is defined elsewhere.


Major ETM architecture version number. A value of 0 in this field indicates ETMv1.

For ETM v3.x, this field = 2.


Minor ETM architecture version number.

For ETM v x.5, this field = 5.


Implementation revision. Value given is for the r0p0 release of the macrocell.

[a] See the Embedded Trace Macrocell Architecture Specification for a definition and list of LSM operations.

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