1.3. Features

ETM-A5 supports tracing of ARM, Thumb, Thumb-EE, and Jazelle instructions.

The Embedded Trace Macrocell Architecture Specification describes the features of ETM v3.5.

Table 1.1 lists the features of the ETM-A5 that are implementation-defined, in terms of either:

Table 1.1. Implementation-specific features of the ETM-A5

FeatureETM-A5 valueNotes
Address comparators4 pairsSee bits [3:0] of the ETMCCR [a]
Data value comparators2See bits [7:4] of the ETMCCR [a]
EmbeddedICE watchpoint comparators0See bits [19:16] of the ETMCCER [b]
Context ID comparators1See bits [25:24] of the ETMCCR [a]
Counters2See bits [15:13] of the ETMCCR [a]
Sequencer1See bit [16] of the ETMCCR [a]
Memory Map decoder inputs0See bits [12:8] of the ETMCCR [a]
External inputs0-4See bits [19:17] of the ETMCCR [a]
External outputs0-2See bits [22:20] of the ETMCCR [a]
Extended external input bus width30See bits [10:3] of the ETMCCER
Extended external input selectors2See bits [2:0] of the ETMCCER [b]
Instrumentation resources0See bits [15:13] of the ETMCCER[b]
Trace port size32-bitSee bits [21,6:4] of the ETMCR [c]
VMID comparator0See bit [26] of the ETMCCER[b]
FIFO size144 bytes-
ASICCTL general-purpose bus interface8-bitSee ASIC Control Register

Table 1.2 shows the optional ETM architecture features the ETM-A5 implements.

Table 1.2. ETM-A5 implementation of optional features

FIFOFULL controlNoSee bit [23] of the ETMCCR [a]
Trace Start/Stop blockYesSee bit [26] of the ETMCCR [a]
Trace all branchesYesSee bit [8] of the ETMCR [b]
Cycle-accurate traceYesSee bit [12] of the ETMCR [b]
Data trace options
 Data address tracingYesSee bits [3:2] of the ETMCR[b]
 Data value tracingYesSee bits [3:2] of the ETMCR [b]
 Data-only tracingYesSee bit [20] of the ETMCR [b]
 CPRT tracingYesSee bits [19, 1] of the ETMCR [b]
TimestampingYesSee bit [28] of the ETMCCER[c]
Data address comparisonYesBit [12] of the ETMCCER [c] reads-as-zero
EmbeddedICE behavior controlNoSee bit [21] of the ETMCCER[c]
EmbeddedICE inputs to Trace Start/Stop blockNoSee bit [20] of the ETMCCER[c]
Alternative address compressionNoSee bit [20] of the ETMIDR
OS Lock mechanismNoSee bits [3, 0] of the ETMOSLSR
Secure non-invasive debugYesSee Embedded Trace Macrocell Architecture Specification
Context ID tracingYesSee bits [15:14] of the ETMCR [b]
VMID tracingNoSee bit [26] of the ETMCCER[c]
Reduced function counterNoSee bit [27] of the ETMCCER[c]

See the Embedded Trace Macrocell Architecture Specification for information about:

See Appendix A Signal Descriptions for information about the macrocell signals.

Copyright © 2009 ARM. All rights reserved.ARM DDI 0435A