3.4. Register summary

This section summarizes the ETM registers. For full descriptions of the ETM registers, see:

Table 3.1 shows all of the registers, and tells you where each register is described in detail. The registers are listed in register number order.

The macrocell registers are listed by functional group in the section Functional grouping of registers. The functional group register tables include additional information about each register:

Note

  • Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.

  • In Table 3.1:

    • the Default value column shows the value of the register immediately after an ETM reset. For read-only registers, every read of the register returns this value.

    • the listed Functional group table gives more information about the register.

    • Access type is described as follows:

      RW

      Read and write.

      RO

      Read only.

      WO

      Write only.

All ETM registers are 32 bits wide.

Table 3.1. ETM-A5 register summary

NumberNameTypeResetGroup [a]Description
0x000ETMCRRW0x000004411ETM Main Control Register
0x001ETMCCRRO0x8D014024 [b]1Configuration Code Register
0x002ETMTRIGGERRW- [c]4Embedded Trace Macrocell Architecture Specification
0x003ETMASICCTLRRW- [c]1ASIC Control Register
0x004ETMSRRW- [c]1Embedded Trace Macrocell Architecture Specification
0x005ETMSCRRO0x00020C0C [d]1Embedded Trace Macrocell Architecture Specification
0x006ETMTSSCRRW- [c]2Embedded Trace Macrocell Architecture Specification
0x007ETMTECR2RW- [c]2Embedded Trace Macrocell Architecture Specification
0x008ETMTEEVRRW- [c]2Embedded Trace Macrocell Architecture Specification
0x009ETMTECR1RW- [c]2Embedded Trace Macrocell Architecture Specification
0x00BETMFFLR[e]RW- [c]1Embedded Trace Macrocell Architecture Specification
0x00CETMVDEVRRW- [c]2Embedded Trace Macrocell Architecture Specification
0x00DETMVDCR1RW- [c]2Embedded Trace Macrocell Architecture Specification
0x00FETMVDCR3RW- [c]2Embedded Trace Macrocell Architecture Specification
0x010 to 0x017ETMACVR1-8RW- [c]3Embedded Trace Macrocell Architecture Specification
0x020 to 0x027ETMACTR1-8RW- [c]3Embedded Trace Macrocell Architecture Specification
0x030[f]ETMDCVR1[f]RW- [c]3Embedded Trace Macrocell Architecture Specification
0x032[f]ETMDCVR3[f]RW- [c]3Embedded Trace Macrocell Architecture Specification
0x040[f]ETMDCMR1[f]RW- [c]3Embedded Trace Macrocell Architecture Specification
0x042[f]ETMDCMR3[f]RW- [c]3Embedded Trace Macrocell Architecture Specification
0x050, 0x051ETMCNTRLDVR1-2RW- [c]4Embedded Trace Macrocell Architecture Specification
0x054, 0x055ETMCNTENR1-2RW- [c]4Embedded Trace Macrocell Architecture Specification
0x058, 0x059ETMCNTRLDEVR1-2RW- [c]4Embedded Trace Macrocell Architecture Specification
0x05C, 0x05DETMCNTVR1-2RW- [c]4Embedded Trace Macrocell Architecture Specification
0x060 to 0x065ETMSQabEVRRW- [c]4Embedded Trace Macrocell Architecture Specification
0x067ETMSQRRW- [c]4Embedded Trace Macrocell Architecture Specification
0x068, 0x069ETMEXTOUTEVR1-2RW- [c]4Embedded Trace Macrocell Architecture Specification
0x06CETMCIDCVRRW- [c]3Embedded Trace Macrocell Architecture Specification
0x06FETMCIDCMRRW- [c]3Embedded Trace Macrocell Architecture Specification
0x078ETMSYNCFRRW0x000004001Embedded Trace Macrocell Architecture Specification
0x079ETMIDRRO0x410CF25x [g]1Embedded Trace Macrocell Architecture Specification
0x07AETMCCERRO0x304008F21Configuration Code Extension Register
0x07BETMEXTINSELRRW- [c]4Extended External Input Selection Register
0x07EETMTSEVRRW- [c]4Embedded Trace Macrocell Architecture Specification
0x07FETMAUXCRRW-1Auxiliary Control Register
0x080ETMTRACEIDRRW0x000000001Embedded Trace Macrocell Architecture Specification
0x082ETMIDR2RO-1ETM ID Register 2
0x0C5ETMPDSRRO- [c]1Power-Down Status Register
0x3B7ITMISCOUTWOn/a [j]6ITMISCOUT Register, miscellaneous outputs
0x3B8ITMISCINRO [h]- [i]6ITMISCIN Register, miscellaneous inputs
0x3BAITTRIGGERREQWOn/a [j]6ITTRIGGERREQ Register, trigger request
0x3BBITATBDATA0WOn/a [j]6ITATBDATA0 Register, ATB data 0
0x3BCITATBCTR2RO [h]- [i]6ITATBCTR2 Register, ATB control 2
0x3BDITATBCTR1WOn/a [j]6ITATBCTR1 Register, ATB control 1
0x3BEITATBCTR0WOn/a [j]6ITATBCTR0 Register, ATB control 0
0x3C0ETMITCTRLRW0x000000005Embedded Trace Macrocell Architecture Specification
0x3E8ETMCLAIMSETRW0x000000FF5Embedded Trace Macrocell Architecture Specification
0x3E9ETMCLAIMCLRRW0x000000005Embedded Trace Macrocell Architecture Specification
0x3ECETMLARWOn/a [j]5Embedded Trace Macrocell Architecture Specification
0x3EDETMLSRRO- [i]5Embedded Trace Macrocell Architecture Specification
0x3EEETMAUTHSTATUSRO- [i]5Embedded Trace Macrocell Architecture Specification
0x3F2ETMDEVIDRO0x000000005Embedded Trace Macrocell Architecture Specification
0x3F3ETMDEVTYPERO0x000000135Embedded Trace Macrocell Architecture Specification
0x3F4 to 0x3F7ETMPIDR4-7RO- [i]5Peripheral Identification Registers
0x3F8 to 0x3FBETMPIDR0-3RO- [i] 
0x3FC to 0x3FFETMCIDR0-3RO- [i]5Component Identification Registers

[a] Functional group. For more information, see:

        for Group 1, Table 3.3

        for Group 2, Table 3.4

        for Group 3, Table 3.5

        for Group 4, Table 3.6

        for Group 5, Table 3.7

        for Group 6, Table 3.8, Table 3.8.

[b] Default value when MAXEXTOUT[1:0] and MAXEXTIN[2:0] are all tied LOW (0), see the register description for more information.

[c] The register is not reset by a reset of the macrocell. Therefore, it does not have a specific default value, and its reset value is Unknown.

[d] Bits [14:12] of the System Configuration Register are tied to the MAXCORES[2:0] signals. If a MAXCORES bit is High then the corresponding bit in the System Configuration Register is set to 1, for example if MAXCORES[0] is tied HIGH then bit [12] is set to 1. The default value given is for all MAXCORES signals tied LOW, bits [14:12] = b000.

For more information about the MAXCORES[2:0] signals, see Signal descriptions

[e] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the Embedded Trace Macrocell Architecture Specification.

[f] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM-A5, reserved areas are:

   Register 0x031, Data Comparator Value 2, at offset 0x0C4     Register 0x033, Data Comparator Value 4, at offset 0x0CC

   Register 0x041, Data Comparator Mask 2, at offset 0x104     Register 0x043, Data Comparator Mask 4, at offset 0x10C.

You must not write to these reserved register addresses. Reads from these addresses are Unpredictable.

[g] The value of bits [3:0] of the ETMIDR depend on the macrocell revision, see ETM ID Register for more information.

[h] The values of the read-only Integration Test registers are valid only when the macrocell is in Integration Test mode. If you read one of these registers when the macrocell is in normal operating mode the result returned is Unknown.

[i] See the register description for details.

[j] Not applicable. These are write-only registers.


Table 3.2 lists the descriptive names of the registers that are described in the Embedded Trace Macrocell Architecture Specification.

Table 3.2. Descriptive names of registers described in the Embedded Trace Macrocell Architecture Specification

Register numberNameDescription
0x002ETMTRIGGERTrigger Event Register
0x004ETMSRETM Status Register
0x005ETMSCRSystem Configuration Register
0x006ETMTSSCRTraceEnable Start/Stop Control Register
0x007ETMTECR2TraceEnable Control 2 Register
0x008ETMTEEVRTraceEnable Event Register
0x009ETMTECR1TraceEnable Control 1 Register
0x00BETMFFLRFIFOFULL Level Register
0x00CETMVDEVRViewData Event Register
0x00DETMVDCR1ViewData Control 1 Register
0x00FETMVDCR3ViewData Control 3 Register
0x010 to 0x017ETMACVR1-8Address Comparator Value Registers 1-8
0x020 to 0x027ETMACTR1-8Address Comparator Access Type Registers 1-8
0x030[f]ETMDCVR1Data Comparator Value Register 1
0x032[f]ETMDCVR3Data Comparator Value Register 3
0x040ETMDCMR1Data Comparator Mask Register 1
0x042ETMDCMRData Comparator Mask Register 3
0x050, 0x051ETMCNTRLDVR1-2Counter Reload Value Registers 1-2
0x054, 0x055ETMCNTENR1-2Counter Enable Registers 1-2
0x058, 0x059ETMCNTRLDEVR1-2Counter Reload Event Registers 1-2
0x05C, 0x05DETMCNTVR1-2Counter Value Registers 1-2
0x060 to 0x065ETMSQabEVRSequencer State Transition Event Registers
0x067ETMSQRCurrent Sequencer State Register
0x068, 0x069ETMEXTOUTEVR1-2External Output Event Registers 1-2
0x06CETMCIDCVRContext ID Comparator Value Register
0x06FETMCIDCMRContext ID Comparator Mask Register
0x078ETMSYNCFRSynchronization Frequency Register
0x080ETMTRACEIDRCoreSight Trace ID Register
0x3C0ETMITCTRLIntegration Mode Control Register
0x3E8ETMCLAIMSETClaim Tag Set Register
0x3E9ETMCLAIMCLRClaim Tag Clear Register
0x3ECETMLARLock Access Register
0x3EDETMLSRLock Status Register
0x3EEETMAUTHSTATUSAuthentication Status Register
0x3F2ETMDEVIDCoreSight Device Configuration Register
0x3F3ETMDEVTYPECoreSight Device Type Register
0x3F4 to 0x3F7ETMPIDR4 to ETMPIDR7Peripheral Identification Registers
0x3F8 to 0x3FBETMPIDR0 to ETMPIDR3
0x3FC to 0x3FFETMCIDR0 to ETMCIDR3Component Identification Registers

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