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This section summarizes the ETM registers. For full descriptions of the ETM registers, see:
Register descriptions, for the implementation-defined registers
the Embedded Trace Macrocell Architecture Specification, for the other registers.
Table 3.1 shows all of the registers, and tells you where each register is described in detail. The registers are listed in register number order.
The macrocell registers are listed by functional group in the section Functional grouping of registers. The functional group register tables include additional information about each register:
The register number.
The register access type, which is read-only, write-only, or read/write.
Additional information about the implementation of the register, where appropriate.
Registers not listed here are not implemented. Reading a non-implemented register address returns 0. Writing to a non-implemented register address has no effect.
In Table 3.1:
the Default value column shows the value of the register immediately after an ETM reset. For read-only registers, every read of the register returns this value.
the listed Functional group table gives more information about the register.
Access type is described as follows:
Read and write.
Read only.
Write only.
All ETM registers are 32 bits wide.
Table 3.1. ETM-A5 register summary
Number | Name | Type | Reset | Group [a] | Description |
---|---|---|---|---|---|
0x000 | ETMCR | RW | 0x00000441 | 1 | ETM Main Control Register |
0x001 | ETMCCR | RO | 0x8D014024 [b] | 1 | Configuration Code Register |
0x002 | ETMTRIGGER | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x003 | ETMASICCTLR | RW | - [c] | 1 | ASIC Control Register |
0x004 | ETMSR | RW | - [c] | 1 | Embedded Trace Macrocell Architecture Specification |
0x005 | ETMSCR | RO | 0x00020C0C [d] | 1 | Embedded Trace Macrocell Architecture Specification |
0x006 | ETMTSSCR | RW | - [c] | 2 | Embedded Trace Macrocell Architecture Specification |
0x007 | ETMTECR2 | RW | - [c] | 2 | Embedded Trace Macrocell Architecture Specification |
0x008 | ETMTEEVR | RW | - [c] | 2 | Embedded Trace Macrocell Architecture Specification |
0x009 | ETMTECR1 | RW | - [c] | 2 | Embedded Trace Macrocell Architecture Specification |
0x00B | ETMFFLR[e] | RW | - [c] | 1 | Embedded Trace Macrocell Architecture Specification |
0x00C | ETMVDEVR | RW | - [c] | 2 | Embedded Trace Macrocell Architecture Specification |
0x00D | ETMVDCR1 | RW | - [c] | 2 | Embedded Trace Macrocell Architecture Specification |
0x00F | ETMVDCR3 | RW | - [c] | 2 | Embedded Trace Macrocell Architecture Specification |
0x010 to 0x017 | ETMACVR1-8 | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x020 to 0x027 | ETMACTR1-8 | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x030 [f] | ETMDCVR1[f] | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x032 [f] | ETMDCVR3[f] | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x040 [f] | ETMDCMR1[f] | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x042 [f] | ETMDCMR3[f] | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x050 , 0x051 | ETMCNTRLDVR1-2 | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x054 , 0x055 | ETMCNTENR1-2 | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x058 , 0x059 | ETMCNTRLDEVR1-2 | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x05C , 0x05D | ETMCNTVR1-2 | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x060 to 0x065 | ETMSQabEVR | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x067 | ETMSQR | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x068 , 0x069 | ETMEXTOUTEVR1-2 | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x06C | ETMCIDCVR | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x06F | ETMCIDCMR | RW | - [c] | 3 | Embedded Trace Macrocell Architecture Specification |
0x078 | ETMSYNCFR | RW | 0x00000400 | 1 | Embedded Trace Macrocell Architecture Specification |
0x079 | ETMIDR | RO | 0x410CF25x [g] | 1 | Embedded Trace Macrocell Architecture Specification |
0x07A | ETMCCER | RO | 0x304008F2 | 1 | Configuration Code Extension Register |
0x07B | ETMEXTINSELR | RW | - [c] | 4 | Extended External Input Selection Register |
0x07E | ETMTSEVR | RW | - [c] | 4 | Embedded Trace Macrocell Architecture Specification |
0x07F | ETMAUXCR | RW | - | 1 | Auxiliary Control Register |
0x080 | ETMTRACEIDR | RW | 0x00000000 | 1 | Embedded Trace Macrocell Architecture Specification |
0x082 | ETMIDR2 | RO | - | 1 | ETM ID Register 2 |
0x0C5 | ETMPDSR | RO | - [c] | 1 | Power-Down Status Register |
0x3B7 | ITMISCOUT | WO | n/a [j] | 6 | ITMISCOUT Register, miscellaneous outputs |
0x3B8 | ITMISCIN | RO [h] | - [i] | 6 | ITMISCIN Register, miscellaneous inputs |
0x3BA | ITTRIGGERREQ | WO | n/a [j] | 6 | ITTRIGGERREQ Register, trigger request |
0x3BB | ITATBDATA0 | WO | n/a [j] | 6 | ITATBDATA0 Register, ATB data 0 |
0x3BC | ITATBCTR2 | RO [h] | - [i] | 6 | ITATBCTR2 Register, ATB control 2 |
0x3BD | ITATBCTR1 | WO | n/a [j] | 6 | ITATBCTR1 Register, ATB control 1 |
0x3BE | ITATBCTR0 | WO | n/a [j] | 6 | ITATBCTR0 Register, ATB control 0 |
0x3C0 | ETMITCTRL | RW | 0x00000000 | 5 | Embedded Trace Macrocell Architecture Specification |
0x3E8 | ETMCLAIMSET | RW | 0x000000FF | 5 | Embedded Trace Macrocell Architecture Specification |
0x3E9 | ETMCLAIMCLR | RW | 0x00000000 | 5 | Embedded Trace Macrocell Architecture Specification |
0x3EC | ETMLAR | WO | n/a [j] | 5 | Embedded Trace Macrocell Architecture Specification |
0x3ED | ETMLSR | RO | - [i] | 5 | Embedded Trace Macrocell Architecture Specification |
0x3EE | ETMAUTHSTATUS | RO | - [i] | 5 | Embedded Trace Macrocell Architecture Specification |
0x3F2 | ETMDEVID | RO | 0x00000000 | 5 | Embedded Trace Macrocell Architecture Specification |
0x3F3 | ETMDEVTYPE | RO | 0x00000013 | 5 | Embedded Trace Macrocell Architecture Specification |
0x3F4 to 0x3F7 | ETMPIDR4-7 | RO | - [i] | 5 | Peripheral Identification Registers |
0x3F8 to 0x3FB | ETMPIDR0-3 | RO | - [i] | ||
0x3FC to 0x3FF | ETMCIDR0-3 | RO | - [i] | 5 | Component Identification Registers |
[a] Functional group. For more information, see: for Group 1, Table 3.3 for Group 2, Table 3.4 for Group 3, Table 3.5 for Group 4, Table 3.6 for Group 5, Table 3.7 [b] Default value when MAXEXTOUT[1:0] and MAXEXTIN[2:0] are all tied LOW (0), see the register description for more information. [c] The register is not reset by a reset of the macrocell. Therefore, it does not have a specific default value, and its reset value is Unknown. [d] Bits [14:12] of the System Configuration Register are tied to the MAXCORES[2:0] signals. If a MAXCORES bit is High then the corresponding bit in the System Configuration Register is set to 1, for example if MAXCORES[0] is tied HIGH then bit [12] is set to 1. The default value given is for all MAXCORES signals tied LOW, bits [14:12] = b000. For more information about the MAXCORES[2:0] signals, see Signal descriptions [e] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the Embedded Trace Macrocell Architecture Specification. [f] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM-A5, reserved areas are: Register Register You must not write to these reserved register addresses. Reads from these addresses are Unpredictable. [g] The value of bits [3:0] of the ETMIDR depend on the macrocell revision, see ETM ID Register for more information. [h] The values of the read-only Integration Test registers are valid only when the macrocell is in Integration Test mode. If you read one of these registers when the macrocell is in normal operating mode the result returned is Unknown. [i] See the register description for details. [j] Not applicable. These are write-only registers. |
Table 3.2 lists the descriptive names of the registers that are described in the Embedded Trace Macrocell Architecture Specification.
Table 3.2. Descriptive names of registers described in the Embedded Trace Macrocell Architecture Specification
Register number | Name | Description |
---|---|---|
0x002 | ETMTRIGGER | Trigger Event Register |
0x004 | ETMSR | ETM Status Register |
0x005 | ETMSCR | System Configuration Register |
0x006 | ETMTSSCR | TraceEnable Start/Stop Control Register |
0x007 | ETMTECR2 | TraceEnable Control 2 Register |
0x008 | ETMTEEVR | TraceEnable Event Register |
0x009 | ETMTECR1 | TraceEnable Control 1 Register |
0x00B | ETMFFLR | FIFOFULL Level Register |
0x00C | ETMVDEVR | ViewData Event Register |
0x00D | ETMVDCR1 | ViewData Control 1 Register |
0x00F | ETMVDCR3 | ViewData Control 3 Register |
0x010 to 0x017 | ETMACVR1-8 | Address Comparator Value Registers 1-8 |
0x020 to 0x027 | ETMACTR1-8 | Address Comparator Access Type Registers 1-8 |
0x030 [f] | ETMDCVR1 | Data Comparator Value Register 1 |
0x032 [f] | ETMDCVR3 | Data Comparator Value Register 3 |
0x040 | ETMDCMR1 | Data Comparator Mask Register 1 |
0x042 | ETMDCMR | Data Comparator Mask Register 3 |
0x050 , 0x051 | ETMCNTRLDVR1-2 | Counter Reload Value Registers 1-2 |
0x054 , 0x055 | ETMCNTENR1-2 | Counter Enable Registers 1-2 |
0x058 , 0x059 | ETMCNTRLDEVR1-2 | Counter Reload Event Registers 1-2 |
0x05C , 0x05D | ETMCNTVR1-2 | Counter Value Registers 1-2 |
0x060 to 0x065 | ETMSQabEVR | Sequencer State Transition Event Registers |
0x067 | ETMSQR | Current Sequencer State Register |
0x068 , 0x069 | ETMEXTOUTEVR1-2 | External Output Event Registers 1-2 |
0x06C | ETMCIDCVR | Context ID Comparator Value Register |
0x06F | ETMCIDCMR | Context ID Comparator Mask Register |
0x078 | ETMSYNCFR | Synchronization Frequency Register |
0x080 | ETMTRACEIDR | CoreSight Trace ID Register |
0x3C0 | ETMITCTRL | Integration Mode Control Register |
0x3E8 | ETMCLAIMSET | Claim Tag Set Register |
0x3E9 | ETMCLAIMCLR | Claim Tag Clear Register |
0x3EC | ETMLAR | Lock Access Register |
0x3ED | ETMLSR | Lock Status Register |
0x3EE | ETMAUTHSTATUS | Authentication Status Register |
0x3F2 | ETMDEVID | CoreSight Device Configuration Register |
0x3F3 | ETMDEVTYPE | CoreSight Device Type Register |
0x3F4 to 0x3F7 | ETMPIDR4 to ETMPIDR7 | Peripheral Identification Registers |
0x3F8 to 0x3FB | ETMPIDR0 to ETMPIDR3 | |
0x3FC to 0x3FF | ETMCIDR0 to ETMCIDR3 | Component Identification Registers |