^[a] Functional group. For more information, see:

        for Group 1, Table 3.3

        for Group 2, Table 3.4

        for Group 3, Table 3.5

        for Group 4, Table 3.6

        for Group 5, Table 3.7

        for Group 6, Table 3.8, Table 3.8.

^[b] Default value when MAXEXTOUT[1:0] and MAXEXTIN[2:0] are all tied LOW (0), see the register description for more information.

^[c] The register is not reset by a reset of the macrocell. Therefore, it does not have a specific default value, and its reset value is Unknown.

^[d] Bits [14:12] of the System Configuration Register are tied to the MAXCORES[2:0] signals. If a MAXCORES bit is High then the corresponding bit in the System Configuration Register is set to 1, for example if MAXCORES[0] is tied HIGH then bit [12] is set to 1. The default value given is for all MAXCORES signals tied LOW, bits [14:12] = b000.

For more information about the MAXCORES[2:0] signals, see Signal descriptions

^[e] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the Embedded Trace Macrocell Architecture Specification.

^[f] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM-A5, reserved areas are:

   Register 0x031, Data Comparator Value 2, at offset 0x0C4     Register 0x033, Data Comparator Value 4, at offset 0x0CC

   Register 0x041, Data Comparator Mask 2, at offset 0x104     Register 0x043, Data Comparator Mask 4, at offset 0x10C.

You must not write to these reserved register addresses. Reads from these addresses are Unpredictable.

^[g] The value of bits [3:0] of the ETMIDR depend on the macrocell revision, see ETM ID Register for more information.

^[h] The values of the read-only Integration Test registers are valid only when the macrocell is in Integration Test mode. If you read one of these registers when the macrocell is in normal operating mode the result returned is Unknown.

^[i] See the register description for details.

^[j] Not applicable. These are write-only registers.