3.4.1. Functional grouping of registers

This section lists the macrocell registers by functional group, as follows:

These functional groups include all of the registers.

Note

All registers are in the CLK clock domain.

General control and ID registers

Table 3.3 shows the general control and ID registers in register number order.

Table 3.3. General control and ID registers

Register numberNameBase offsetDescription
0x000ETM Control0x000ETM Main Control Register
0x001Configuration Code0x004Configuration Code Register
0x003ASIC Control0x00CASIC Control Register
0x004ETM Status0x010Embedded Trace Macrocell Architecture Specification
0x005System Configuration0x014Embedded Trace Macrocell Architecture Specification
0x00BFIFOFULL Level[a]0x02CEmbedded Trace Macrocell Architecture Specification
0x078Synchronization Frequency0x1E0Embedded Trace Macrocell Architecture Specification
0x079ETM ID0x1E4ETM ID Register
0x07AConfiguration Code Extension0x1E8Configuration Code Extension Register
0x07FAuxiliary Control0x1FCAuxiliary Control Register
0x080CoreSight Trace ID0x200ETM Architecture Specification
0x082CoreSight Trace ID0x208ETM ID Register 2
0x0C5Power-Down Status 0x314Power-Down Status Register

[a] Although the macrocell does not include FIFOFULL logic, the FIFOFULL Level Register controls the FIFO level at which data suppression occurs. For more information see the Embedded Trace Macrocell Architecture Specification.


TraceEnable and ViewData registers

Table 3.4 shows the TraceEnable and ViewData registers in register number order.

Table 3.4. TraceEnable and ViewData registers

Register numberNameBase offsetDescription
0x006TraceEnable Start/Stop Resource control0x018Embedded Trace Macrocell Architecture Specification
0x007TraceEnable Control 20x01CEmbedded Trace Macrocell Architecture Specification
0x008TraceEnable Event0x020Embedded Trace Macrocell Architecture Specification
0x009TraceEnable Control 10x024Embedded Trace Macrocell Architecture Specification
0x00CViewData Event0x030Embedded Trace Macrocell Architecture Specification
0x00DViewData Control 10x034Embedded Trace Macrocell Architecture Specification
0x00FViewData Control 30x03CEmbedded Trace Macrocell Architecture Specification

Comparator registers

Table 3.5 shows the comparator registers in register number order. These control the Address, Data, and Context ID comparators.

Table 3.5. Comparator registers

Register numberNameBase offsetDescription
0x010 to 0x017Address Comparator Value 1 - 80x040 to 0x05FEmbedded Trace Macrocell Architecture Specification
0x020 to 0x027Address Comparator Access Type 1 - 80x080 to 0x09FEmbedded Trace Macrocell Architecture Specification
0x030 [a]Data Comparator Value 1 [a]0x0C0 [a]Embedded Trace Macrocell Architecture Specification
0x032 [a]Data Comparator Value 3 [a]0x0C8 [a]Embedded Trace Macrocell Architecture Specification
0x040 [a]Data Comparator Mask 1 [a]0x100 [a]Embedded Trace Macrocell Architecture Specification
0x042 [a]Data Comparator Mask 3 [a]0x108 [a]Embedded Trace Macrocell Architecture Specification
0x06CContext ID Comparator Value0x1B0Embedded Trace Macrocell Architecture Specification
0x06FContext ID Comparator Mask0x1BCEmbedded Trace Macrocell Architecture Specification

[a] In the Data Comparator register area, even number registers are reserved. For the CoreSight ETM-A5, reserved areas are:

   Register 0x031, Data Comparator Value 2, at offset 0x0C4     Register 0x033, Data Comparator Value 4, at offset 0x0CC

   Register 0x041, Data Comparator Mask 2, at offset 0x104     Register 0x043, Data Comparator Mask 4, at offset 0x10C.

You must not write to these reserved register addresses. The value of a reads from these addresses is Unknown.


Counter, sequencer and other resource registers

Table 3.6 shows the counter, sequencer and other resource registers in register number order. These control:

  • the two counters, and associated events

  • the sequencer, and associated state change events

  • Trigger events

  • EXTOUT (External Output) events

  • Extended External Input selection.

Table 3.6. Counter, sequencer and other resource registers

Register numberNameBase offsetDescription
0x002Trigger Event0x008Embedded Trace Macrocell Architecture Specification
0x050, 0x051Counter Reload Value 1 - 20x140, 0x144Embedded Trace Macrocell Architecture Specification
0x054, 0x055Counter Enable Event 1 - 20x150, 0x154Embedded Trace Macrocell Architecture Specification
0x058, 0x059Counter Reload Event 1 - 20x160, 0x164Embedded Trace Macrocell Architecture Specification
0x05C, 0x05DCounter Value 1 - 20x170, 0x174Embedded Trace Macrocell Architecture Specification
0x060 to 0x065Sequencer State Transition Events0x180 to 0x194Embedded Trace Macrocell Architecture Specification
0x067Current Sequencer State0x19CEmbedded Trace Macrocell Architecture Specification
0x068, 0x069External Output Event 1 - 20x1A0, 0x1A4Embedded Trace Macrocell Architecture Specification
0x07BExtended External Input Selector0x1ECExtended External Input Selection Register
0x07ETimestamp Event0x1F8Embedded Trace Macrocell Architecture Specification

CoreSight management registers

Table 3.7 shows the CoreSight management registers in register number order.

Table 3.7. CoreSight management registers

Register numberNameBase offsetDescription
0x3C0Integration Mode Control0xF00Embedded Trace Macrocell Architecture Specification
0x3E8Claim Tag Set0xFA0Embedded Trace Macrocell Architecture Specification
0x3E9Claim Tag Clear0xFA4Embedded Trace Macrocell Architecture Specification
0x3ECLock Access0xFB0Embedded Trace Macrocell Architecture Specification
0x3EDLock Status0xFB4Embedded Trace Macrocell Architecture Specification
0x3EEAuthentication Status0xFB8Embedded Trace Macrocell Architecture Specification
0x3F2Device Configuration0xFC8Embedded Trace Macrocell Architecture Specification
0x3F3Device Type0xFCCEmbedded Trace Macrocell Architecture Specification
0x3F4 to 0x3F7Peripheral ID4 to 70xFD0 to 0xFDCPeripheral Identification Registers
0x3F8 to 0x3FBPeripheral ID0 to 30xFE0 to 0xFEC
0x3FC to 0x3FFComponent ID0 to 30xFF0 to 0xFFCComponent Identification Registers

Integration test registers

Table 3.8 shows the integration test registers in register number order.

Table 3.8. Integration test registers

Register numberNameBase offsetDescription
0x3B7ITMISCOUT0xEDCITMISCOUT Register, miscellaneous outputs
0x3B8ITMISCIN0xEE0ITMISCIN Register, miscellaneous inputs
0x3BAITTRIGGERREQ0xEE8ITTRIGGERREQ Register, trigger request
0x3BBITATBDATA00xEECITATBDATA0 Register, ATB data 0
0x3BCITATBCTR20xEF0ITATBCTR2 Register, ATB control 2
0x3BDITATBCTR10xEF4ITATBCTR1 Register, ATB control 1
0x3BEITATBCTR00xEF8ITATBCTR0 Register, ATB control 0

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