2.4.6. Interaction with the Performance Monitoring Unit (PMU)

The Cortex-A5 processor includes a PMU that enables events, such as cache misses and instructions executed, to be counted over a period of time. The macrocell can still use these events by means of the extended external input facility. Each bit in the EVNTBUS[29:0] input is mapped to the corresponding extended external input. See the Cortex-A5 Technical Reference Manual for details of the mapping of events to bits within this bus.

The Cortex-A5 PMU can count the two external outputs as additional events. These events are not provided back to the macrocell as extended external inputs.

These facilities enable additional filtering of the system events using ETM resources, such as instruction address ranges or the start/stop resource, before they are passed back to the PMU for counting. To do this:

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