2.2. Interfaces

The ETM-A5 macrocell has the following external interfaces:

ATB

A 32-bit ATB, used for trace output from the macrocell. See the AMBA™ 3 ATB Protocol Specification for more information about this interface.

APB

An APB provides the control interface for the macrocell. See the AMBA™ 3 APB Protocol Specification for more information about this interface.

Cortex-A5 ETM interface

The Cortex-A5 processor passes its execution information to the ETM-A5 over this bus. This includes instruction address, branch, exception, data address, data value and Performance Monitoring Unit information.

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