2.3.2. Clock enable signals

ETM-A5 has the following clock enable signals:


This is the ATB clock enable. The ATB can be operated using a slower clock, ATCLK, generated by dividing CLK. The ATCLKEN clock enable must be asserted for one CLK cycle on each rising edge of ATCLK.


This is the Debug APB interface clock enable. It can slow down PCLKDBG.

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