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The following subsections describe the Integration Test Registers. To access these registers, set bit [0] of the Integration Mode Control Register (ETMITCTRL) to 1.
You can use the write-only Integration Test Registers to set the outputs of some of the ETM signals. Table 3.20 shows the signals that can be controlled in this way.
You can use the read-only Integration Test Registers to read the state of some of the ETM input signals. Table 3.21 shows the signals that can be read in this way.
See the Embedded Trace Macrocell Architecture Specification for more information on ETMITCTRL.
Table 3.20. Output signals that the Integration Test Registers can control
| Signal | Register | Bits | Register description |
|---|---|---|---|
| AFREADY | ITATBCTR0 | [1] | See ITATBCTR0 Register, ATB control 0 |
| ATBYTES[1:0] | ITATBCTR0 | [9:8] | See ITATBCTR0 Register, ATB control 0 |
| ATDATA[31, 23, 15, 7, 0] | ITATBDATA0 | [4:0] | See ITATBDATA0 Register, ATB data 0 |
| ATID[6:0] | ITATBCTR1 | [6:0] | See ITATBCTR1 Register, ATB control 1 |
| ATVALID | ITATBCTR0 | [0] | See ITATBCTR0 Register, ATB control 0 |
| ETMDBGRQ | ITMISCOUT | [4] | See ITMISCOUT Register, miscellaneous outputs |
| ETMSTANDBYWFX | ITMISCOUT | [5] | See ITMISCOUT Register, miscellaneous outputs |
| EXTOUT[1:0] | ITMISCOUT | [9:8] | See ITMISCOUT Register, miscellaneous outputs |
| SYNCREQ | ITATBCTR2 | [2] | See ITATBCTR2 Register, ATB control 2 |
| TRIGGER | ITTRIGGERREQ | [0] | See ITTRIGGERREQ Register, trigger request |
Table 3.21. Input signals that the Integration Test Registers can read
| Signal | Register | Bits | Register description |
|---|---|---|---|
| AFVALID | ITATBCTR2 | [1] | See ITATBCTR2 Register, ATB control 2 |
| ATREADY | ITATBCTR2 | [0] | See ITATBCTR2 Register, ATB control 2 |
| DBGACK | ITMISCIN | [4] | See ITMISCIN Register, miscellaneous inputs |
| ETMWFXPENDING | ITMISCIN | [5] | See ITMISCIN Register, miscellaneous inputs |
| EXTIN[3:0] | ITMISCIN | [3:0] | See ITMISCIN Register, miscellaneous inputs |
The CoreSight ETM-A5 Integration Manual gives a full description of the use of the Integration Test Registers to check integration. In brief:
When bit [0] of ETMITCTRL is set to 1:
Values written to the write-only
integration test registers map onto the specified outputs of the
macrocell. For example, writing 0x3 to ITMISCOUT[9:8]
causes EXTOUT[1:0] to take the
value 0x3.
Values read from the read-only integration test registers correspond to the values of the specified inputs of the macrocell. For example, if you read ITMISCIN[3:0] you obtain the value of EXTIN[3:0].
When bit [0] of ETMITCTRL is set to 0:
Reading an Integration Test Register returns an Unpredictable value.
The effect of attempting to write to an Integration Test Register, other than the read-only Integration Test Registers, is Unpredictable.
You must not attempt to write to an Integration Test Register unless you have set bit [0] of ETMITCTRL to 1.
See the Embedded Trace Macrocell Architecture Specification for details of ETMITCTRL.
The ITMISCOUT characteristics are:
Sets the state of the output pins shown in Table 3.22.
Available when bit [0] of ETMITCTRL is set to 1
The value of the register sets the signals on the output pins when the register is written.
Always available.
See the register summaries in Table 3.1, Table 3.8, and Table 3.21.
Figure 3.13 shows the ITMISCOUT bit assignments.
Table 3.22 shows the ITMISCOUT bit assignments.
Table 3.22. ITMISCOUT bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:10] | - | Reserved. Write as zero. |
| [9:8] | EXTOUT | Drives the EXTOUT[1:0] output pins[a]. |
| [7:6] | - | Reserved. Write as zero. |
| [5] | ETMWFXREADY | Drives the nETMWFXREADY output pin[a]. |
| [4] | ETMDBGRQ | Drives the ETMDBGRQ output pin[a]. |
| [3:0] | - | Reserved. Write as zero. |
[a] When a bit is set to 0, the corresponding output pin is LOW. When a bit is set to 1, the corresponding output pin is HIGH. The ITMISCOUT bit values correspond to the physical state of the output pins. | ||
The ITMISCIN characteristics are:
Reads the state of the input pins shown in Table 3.23
Available when bit [0] of ETMITCTRL is set to 1
The values of the register bits depend on the signals on the input pins when the register is read.
Always available.
See the register summaries in Table 3.1, Table 3.8, and Table 3.21.
Figure 3.14 shows the ITMISCIN bit assignments.
Table 3.23 shows the ITMISCIN bit assignments.
Table 3.23. ITMISCIN bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:6] | - | Reserved. Read undefined. |
| [5] | ETMWFXPENDING | Returns the value of the ETMWFXPENDING input pin[a]. |
| [4] | DBGACK | Returns the value of the DBGACK input pin[a]. |
| [3:0] | EXTIN | Returns the value of the EXTIN[3:0] input pins[a]. |
[a] When a bit is set to 0, the corresponding input pin is LOW. When a bit is set to 1, the corresponding input pin is HIGH. The ITMISCIN bit values always correspond to the physical state of the input pins. | ||
The ITTRIGGERREQ characteristics are:
Sets the TRIGGER output pin shown in Table 3.24.
Available when bit [0] of ETMITCTRL is set to 1
The values of the register bits set the signals on the output pin when the register is written.
Always available.
See the register summaries in Table 3.1, Table 3.8, and Table 3.21.
Figure 3.15 shows the ITTRIGGERREQ bit assignments.
Table 3.24 shows the ITTRIGGERREQ bit assignments.
Table 3.24. ITTRIGGERREQ bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:1] | - | Reserved. Write as zero. |
| [0] | TRIGGER | Drives the TRIGGER output pin[a]. |
[a] When a bit is set to 0, the corresponding output pin is LOW. When a bit is set to 1, the corresponding output pin is HIGH. The ITTRIGGERREQ bit values always correspond to the physical state of the output pins. | ||
The ITATBDATA0 characteristics are:
Sets the state of the ATDATA output pins shown in Table 3.25.
Available when bit [0] of ETMITCTRL is set to 1
The values of the register bits set the signals on the output pins when the register is written.
Always available.
See the register summaries in Table 3.1, Table 3.8, and Table 3.21.
Figure 3.16 shows the ITATBDATA0 bit assignments.
Table 3.25 shows the ITATBDATA0 bit assignments.
Table 3.25. ITATBDATA0 bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:5] | - | Reserved. Write as zero. |
| [4:0] | ATDATA | Drives the ATDATA[31, 23, 15, 7, 0] output pins[a]. |
[a] When a bit is set to 0, the corresponding output pin is LOW. When a bit is set to 1, the corresponding output pin is HIGH. The ITATBDATA0 bit values always correspond to the physical state of the output pins. | ||
The ITATBCTR2 characteristics are:
Reads the state of the AFVALID, ATREADY, and SYNCREQ input pins from the ATB bus, as shown in Table 3.26.
Available when bit [0] of ETMITCTRL is set to 1
The values of the register bits depend on the signals on the input pins when the register is read.
Always available.
See the register summaries in Table 3.1, Table 3.8, and Table 3.21.
Figure 3.17 shows the ITATBCTR2 bit assignments.
Table 3.26 shows the ITATBCTR2 bit assignments.
Table 3.26. ITATBCTR2 bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:3] | - | Reserved. Read undefined. |
| [2] | SYNCREQ | Returns the value of the SYNCREQ input pin |
| [1] | AFVALID | Returns the value of the AFVALID input pin[a]. |
| [0] | ATREADY | Returns the value of the ATREADY input pin[a]. |
[a] When a bit is set to 0, the corresponding input pin is LOW. When a bit is set to 1, the corresponding input pin is HIGH. The ITATBCTR2 bit values always correspond to the physical state of the input pins. | ||
The ITATBCTR1 characteristics are:
Sets the state of the ATID output pins shown in Table 3.27.
Available when bit [0] of ETMITCTRL is set to 1
The values of the register bits set the signals on the output pins when the register is written.
Always available.
See the register summaries in Table 3.1, Table 3.8, and Table 3.21.
Figure 3.18 shows the ITATBCTR1 bit assignments.
Table 3.27 shows the ITATBCTR1 bit assignments.
Table 3.27. ITATBCTR1 bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:7] | - | Reserved. Write as zero. |
| [6:0] | ATID | Drives the ATID[6:0] output pins[a]. |
[a] When a bit is set to 0, the corresponding output pin is LOW. When a bit is set to 1, the corresponding output pin is HIGH. The ITATBCTR1 bit values always correspond to the physical state of the output pins. | ||
The ITATBCTR0 characteristics are:
Sets the state of the output pins shown in Table 3.28.
Available when bit [0] of ETMITCTRL is set to 1
The values of the register bits set the signals on the output pins when the register is written.
Always available.
See the register summaries in Table 3.1, Table 3.8, and Table 3.21.
Figure 3.19 shows the ITATBCTR0 bit assignments.
Table 3.28 shows the ITATBCTR0 bit assignments.
Table 3.28. ITATBCTR0 bit assignments
| Bits | Name | Description |
|---|---|---|
| [31:10] | - | Reserved. Write as zero. |
| [9:8] | ATBYTES | Drives the ATBYTES[1:0] output pins[a]. |
| [7:2] | - | Reserved. Write as zero. |
| [1] | AFREADY | Drives the AFREADY output pin[a]. |
| [0] | ATVALID | Drives the ATVALID output pin[a]. |
[a] When a bit is set to 0, the corresponding output pin is LOW. When a bit is set to 1, the corresponding output pin is HIGH. The ITATBCTR0 bit values always correspond to the physical state of the output pins. | ||
| Copyright © 2009 ARM. All rights reserved. | ARM DDI 0435A |
| Non-Confidential | |
| PDF version | |
| Home > Programmers Model > Register descriptions > Integration Test Registers |