CoreSight ETM-A5 Technical Reference Manual: 1.3. Features

1.3. Features

ETM-A5 supports tracing of ARM, Thumb, Thumb-EE, and Jazelle instructions.

The Embedded Trace Macrocell Architecture Specification describes the features of ETM v3.5.

Table 1.1 lists the features of the ETM-A5 that are implementation-defined, in terms of either:

Table 1.1. Implementation-specific features of the ETM-A5

Feature	ETM-A5 value	Notes
Address comparators	4 pairs	See bits [3:0] of the ETMCCR ^[a]
Data value comparators	2	See bits [7:4] of the ETMCCR ^[a]
EmbeddedICE watchpoint comparators	0	See bits [19:16] of the ETMCCER ^[b]
Context ID comparators	1	See bits [25:24] of the ETMCCR ^[a]
Counters	2	See bits [15:13] of the ETMCCR ^[a]
Sequencer	1	See bit [16] of the ETMCCR ^[a]
Memory Map decoder inputs	0	See bits [12:8] of the ETMCCR ^[a]
External inputs	0-4	See bits [19:17] of the ETMCCR ^[a]
External outputs	0-2	See bits [22:20] of the ETMCCR ^[a]
Extended external input bus width	30	See bits [10:3] of the ETMCCER
Extended external input selectors	2	See bits [2:0] of the ETMCCER ^[b]
Instrumentation resources	0	See bits [15:13] of the ETMCCER^[b]
Trace port size	32-bit	See bits [21,6:4] of the ETMCR ^[c]
VMID comparator	0	See bit [26] of the ETMCCER^[b]
FIFO size	144 bytes	-
ASICCTL general-purpose bus interface	8-bit	See ASIC Control Register
^[a]See Configuration Code Register. ^[b]See Configuration Code Extension Register. ^[c]See ETM Main Control Register.

Table 1.2 shows the optional ETM architecture features the ETM-A5 implements.

Table 1.2. ETM-A5 implementation of optional features

Feature		Implemented	Notes
FIFOFULL control		No	See bit [23] of the ETMCCR ^[a]
Trace Start/Stop block		Yes	See bit [26] of the ETMCCR ^[a]
Trace all branches		Yes	See bit [8] of the ETMCR ^[b]
Cycle-accurate trace		Yes	See bit [12] of the ETMCR ^[b]
Data trace options
	Data address tracing	Yes	See bits [3:2] of the ETMCR^[b]
	Data value tracing	Yes	See bits [3:2] of the ETMCR ^[b]
	Data-only tracing	Yes	See bit [20] of the ETMCR ^[b]
	CPRT tracing	Yes	See bits [19, 1] of the ETMCR ^[b]
Timestamping		Yes	See bit [28] of the ETMCCER^[c]
Data address comparison		Yes	Bit [12] of the ETMCCER ^[c] reads-as-zero
EmbeddedICE behavior control		No	See bit [21] of the ETMCCER^[c]
EmbeddedICE inputs to Trace Start/Stop block		No	See bit [20] of the ETMCCER^[c]
Alternative address compression		No	See bit [20] of the ETMIDR
OS Lock mechanism		No	See bits [3, 0] of the ETMOSLSR
Secure non-invasive debug		Yes	See Embedded Trace Macrocell Architecture Specification
Context ID tracing		Yes	See bits [15:14] of the ETMCR ^[b]
VMID tracing		No	See bit [26] of the ETMCCER^[c]
Reduced function counter		No	See bit [27] of the ETMCCER^[c]
^[a]See Configuration Code Register. ^[b]See ETM Main Control Register. ^[c]See Configuration Code Extension Register.

See the Embedded Trace Macrocell Architecture Specification for information about:

See Appendix A Signal Descriptions for information about the macrocell signals.

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