CoreSight ETM-A5 Technical Reference Manual: 3.5.1. ETM Main Control Register

3.5.1. ETM Main Control Register

The ETMCR characteristics are:

Purpose: Controls general operation of the ETM, such as whether tracing is enabled or coprocessor data is traced.
Usage constraints: There are no usage constraints.
Configurations: Always available.
Attributes: See the register summary in Table 3.1 and Table 3.3.

Figure 3.1 shows the ETMCR bit assignments.

Figure 3.1. ETMCR bit assignments

Table 3.9 shows the ETMCR bit assignments.

Table 3.9. ETMCR bit assignments

Bits	Name	Access	Description
[31:29]	Reserved	RW	Must be written as 0.
[28]	Enable timestamping	RW	Set to 1 to enable timestamping. On an ETM reset this bit is 0.
[27:25]	Core select	RW	If an ETM is shared between multiple cores, selects which core to trace. For the maximum value permitted, see bits [14:12] of the System Configuration Register. See the Embedded Trace Macrocell Architecture Specification for more information. To guarantee that the ETM is correctly synchronized to the new core, you must update these bits as follows: Set bit [10], ETM programming, and bit [0], ETM power down, to 1. Change the core select bits. Clear bit [0], ETM power down, to 0. Perform other programming required as normal. On an ETM reset this field is zero.
[24]	Instrumentation resources access control	RO	ETM-A5 does not implement any instrumentation resources and therefore this bit is RAZ.
[23]	Disable software writes	RO	ETM-A5 does not support this feature and therefore this bit is RAZ.
[22]	Disable register writes from the debugger	RO	ETM-A5 does not support this feature and therefore this bit is RAZ.
[21]	Port size[3]	RW	Use this bit in conjunction with bits [6:4]. On an ETM reset this bit is 0, corresponding to the 32-bit port size.
[20]	Data-only mode	RW	The possible values of this bit are: 0 Instruction trace enabled. 1 Instruction trace disabled. Data-only tracing is possible in this mode. On an ETM reset this bit is 0.
[19]	Filter (CPRT)	RW	Use this bit in conjunction with bit [1], the MonitorCPRT bit. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification. On an ETM reset this bit is 0.
[18]	Suppress data	RW	Use this bit with bit [7] to suppress data. For details see Data suppression in the Embedded Trace Macrocell Architecture Specification. On an ETM reset this bit is 0.
[17:16]	Port mode[1:0]	RW	These bits are used, in conjunction with bit [13], to set the trace port clocking mode. ETM-A5 supports only dynamic mode, corresponding to the value b000, but you can write other values to these bits, and a read of the register returns the value written. Writing another value to these bits has no effect on the ETM. Bit [11] of the System Configuration Register indicates if these bits are set to select a supported clocking mode. On an ETM reset these bits are zero. For more information about trace port clocking modes see the Embedded Trace Macrocell Architecture Specification.
[15:14]	ContextIDsize	RW	The possible values of this field are: b00 No Context ID tracing. b01 Context ID bits [7:0] traced. b10 Context ID bits [15:0] traced. b11 Context ID bits [31:0] traced. Note Only the number of bytes specified is traced even if the new value is larger than this. On an ETM reset this field is zero.
[13]	Port mode[2]	RW	See the description of bits [17:16]. On an ETM reset this bit is 0.
[12]	Cycle-accurate tracing	RW	Set this bit to 1 if you want the trace to include a precise cycle count of executed instructions. This is achieved by adding extra information into the trace, giving cycle counts even when TraceEnable is inactive. On an ETM reset this bit is 0.
[11]	ETM port selection	RW	This bit controls an external output, ETMEN. The possible values are: 0 ETMEN is LOW. 1 ETMEN is HIGH. You can use the ETMEN signal to control the routing of trace port signals to shared GPIO pins on your SoC, under the control of logic external to the ETM. Trace software tools must set this bit to 1 to ensure that trace output is enabled from this ETM. On an ETM reset this bit is 0.
[10]	ETM programming	RW	When set to 1, the ETM is being programmed. For more information, see ETM Programming bit and associated state in the Embedded Trace Macrocell Architecture Specification. On an ETM reset this bit is set to b1.
[9]	Debug request control	RW	If you set this bit to 1, when the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the Cortex-A5 processor to be forced into Debug state. On an ETM reset this bit is 0.
[8]	Branch output	RW	Set this bit to 1 if you want the ETM to output all branch addresses, even if the branch is because of a direct branch instruction. Setting this bit to 1 enables reconstruction of the program flow without having access to the memory image of the code being executed. On an ETM reset this bit is 0.
[7]	Stall processor	RO	ETM-A5 does not implement FIFOFULL stalling of the processor, and therefore this bit is RAZ.
[6:4]	Port size[2:0]	RW	Use this field with bit [21] to specify the port size. The port size determines how many external pins are available to output the trace information on ATDATA[31:0]. ETM-A5 supports only the 32-bit port size, corresponding to a Port size[3:0] value of b0100, but you can write other values to these bits, and a read of the register returns the value written. Writing other values to these bits has no effect on the ETM. Bit [10] of the System Configuration Register indicates if these bits are set to select an unsupported port size. For more information see the Embedded Trace Macrocell Architecture Specification. On an ETM reset this field is b100, corresponding to the 32-bit port size.
[3:2]	Data access	RW	This field configures the data tracing mode. The possible values are: b00 No data tracing. b01 Trace only the data portion of the access. b10 Trace only the address portion of the access. b11 Trace both the address and the data of the access. On an ETM reset this field is zero.
[1]	MonitorCPRT	RW	This field controls whether CPRTs are traced. The possible values are: 0 CPRTs not traced. 1 CPRTs traced. This bit is used with bit [19]. For details see Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later in the Embedded Trace Macrocell Architecture Specification. On an ETM reset this bit is 0.
[0]	ETM power down	RW	A pin controlled by this bit enables the ETM power to be controlled externally, see Control of ETM power down. The sense of this bit is inverted, and drives the ETMPWRUP signal. This bit must be cleared by the trace software tools at the beginning of a debug session. When this bit is set to 1, ETM tracing is disabled and accesses to any registers other than this register and the Lock Access Register are ignored. On an ETM reset this bit is set to 1. See Control of ETM power down for additional information on controlling ETM power down.

Control of ETM power down

You can use the ETMPWRUP signal, controlled by the ETM power down bit of the ETMCR, to gate the clock to the logic in the ETM interface of the processor, to save power. Also, when you set the ETM power down bit to 1, the clock to most of the logic in the ETM is gated, disabling ETM tracing and leaving the ETM block operating in a low-power mode.

Note

You must not use the ETMEN signal to gate the ETM clock or any other functionality required for basic operation. You can use the ETMEN signal to control functionality that is required only for off-chip tracing, such as multiplexing between two ETMs. Use the ETMPWRUP signal to control basic operation of the ETM.

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