AMBA® LPDDR2 Dynamic Memory Controller DMC-342 Technical Reference Manual

Revision: r0p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Additional reading
Feedback
Feedback on this product
Feedback on content
1. Introduction
1.1. About the AMBA LPDDR2 DMC-342
1.2. Compliance
1.3. Features
1.4. Interfaces
1.5. Configurable options
1.6. Test features
1.7. Product documentation, design flow, and architecture
1.7.1. Documentation
1.7.2. Design flow
1.7.3. ARM architecture and protocol information
1.8. Product revisions
2. Functional Description
2.1. About the functions
2.2. Interfaces
2.2.1. AXI slave interface
2.2.2. AXI low-power interface
2.2.3. APB slave interface
2.2.4. Tie-off signals
2.2.5. User signals
2.2.6. Memory interface
2.2.7. DFI pad interface
2.2.8. QoS signal
2.3. Clocking and resets
2.3.1. Clocking
2.3.2. Reset
2.4. Operation
2.4.1. AXI slave interface
2.4.2. AXI low-power interface
2.4.3. APB slave interface
2.4.4. Tie-off signals
2.4.5. Miscellaneous signals
2.4.6. Arbiter
2.4.7. Memory manager
2.4.8. Memory interface
2.4.9. DFI pad interface
2.4.10. Initialization
2.4.11. Power-down support
2.4.12. Power-down usage model
2.5. Constraints and limitations of use
2.5.1. TrustZone Technology Support
2.5.2. Supported memory devices
3. Programmers Model
3.1. About the programmers model
3.1.1. Register map
3.2. Register summary
3.3. Register descriptions
3.3.1. Memory Controller Status Register
3.3.2. Memory Controller Command Register
3.3.3. Direct Command Register
3.3.4. Memory Configuration Register
3.3.5. Refresh Period Register
3.3.6. CAS Latency Register
3.3.7. Write Latency Register
3.3.8. MODEREG to Command Timing Register
3.3.9. ACTIVE to PRECHARGE Timing Register
3.3.10. ACTIVE to ACTIVE Timing Register
3.3.11. ACTIVE to Read or Write Timing Register
3.3.12. AUTO REFRESH to Command Timing Register
3.3.13. PRECHARGE to Command Timing Register
3.3.14. ACTIVE to ACTIVE Different Bank Timing Register
3.3.15. Write to PRECHARGE Timing Register
3.3.16. Write to Read Timing Register
3.3.17. Exit Power-down Timing Register
3.3.18. Exit Self-refresh Timing Register
3.3.19. Self-refresh to Command Timing Register
3.3.20. Memory Configuration 2 Register
3.3.21. Memory Configuration 3 Register
3.3.22. Four Activate Window Timing Register
3.3.23. Update Type Register
3.3.24. Read Data Enable Timing Register
3.3.25. Write Data Enable Timing Register
3.3.26. Read to PRECHARGE Timing Register
3.3.27. Read Mode Register
3.3.28. Clock Enable Register
3.3.29. DFI Initialize Register
3.3.30. Mode Read Data Register
3.3.31. Refresh Control Register
3.3.32. Read Transfer Delay Register
3.3.33. Read Write Delay Register
3.3.34. QoS Configuration registers
3.3.35. Chip Configuration registers
3.3.36. User Status Register
3.3.37. User Config 0 Register
3.3.38. User Config 1 Register
3.3.39. Feature Control Register
3.3.40. Integration Configuration Register
3.3.41. Integration Inputs Register
3.3.42. Integration Outputs Register
3.3.43. Peripheral Identification registers
3.3.44. Component Identification registers
A. Signal Descriptions
A.1. Clock and reset signals
A.2. Miscellaneous signals
A.2.1. QoS
A.2.2. Tie-offs
A.2.3. User signals
A.2.4. Scan test
A.3. AXI signals
A.3.1. Write address channel signals
A.3.2. Write data channel signals
A.3.3. Write response channel signals
A.3.4. Read address channel signals
A.3.5. Read data channel signals
A.3.6. AXI low-power interface signals
A.4. APB signals
A.5. DFI pad interface signals
B. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Example system
2.1. Block diagram
2.2. LPDDR2 DMC interfaces
2.3. AXI slave interface signals
2.4. AXI low-power interface channel signals
2.5. APB interface
2.6. Tie-off signals
2.7. User signals
2.8. mclk domain state diagram
2.9. DFI pad interface signals
2.10. QoS signal
2.11. aclk domain state diagram
2.12. ACTIVE command to Read or Write command timing, tRCD
2.13. Four activate window command timing, tFAW
2.14. Same bank ACTIVE to ACTIVE, and ACTIVE to AUTO REFRESH command timing, tRC
2.15. Different bank ACTIVE to ACTIVE command timing, tRRD
2.16. PRECHARGE to command and AUTO REFRESH to command timing, tRP and tRFC
2.17. ACTIVE to PRECHARGE, and PRECHARGE to PRECHARGE timing, tRAS and tRP
2.18. MODEREG to command timing, tMRD
2.19. Self-refresh entry and exit timing, tESR and tXSR
2.20. Power-down entry and exit timing, tXP
2.21. Data output timing, tWTR
2.22. Write to PRECHARGE timing, tWR
2.23. Data input timing
2.24. Auto power-down
2.25. aclk FSM and power state transitions
2.26. LPDDR2 DMC in context
3.1. Register map
3.2. Configuration register map
3.3. QoS register map
3.4. Chip configuration register map
3.5. User register map
3.6. Integration test register map
3.7. Component configuration register map
3.8. memc_status Register bit assignments
3.9. memc_cmd Register bit assignments
3.10. direct_cmd Register bit assignments
3.11. memory_cfg Register bit assignments
3.12. refresh_prd Register bit assignments
3.13. cas_latency Register bit assignments
3.14. write_latency Register bit assignments
3.15. t_mrd Register bit assignments
3.16. t_ras Register bit assignments
3.17. t_rc Register bit assignments
3.18. t_rcd Register bit assignments
3.19. t_rfc Register bit assignments
3.20. t_rp Register bit assignments
3.21. t_rrd Register bit assignments
3.22. t_wr Register bit assignments
3.23. t_wtr Register bit assignments
3.24. t_xp Register bit assignments
3.25. t_xsr Register bit assignments
3.26. t_esr Register bit assignments
3.27. memory_cfg2 Register bit assignments
3.28. memory_cfg3 Register bit assignments
3.29. t_faw Register bit assignments
3.30. t_phyupd_type Register bit assignments
3.31. t_rddata_en Register bit assignments
3.32. t_phywrlat Register bit assignments
3.33. t_rtp Register bit assignments
3.34. t_mrr Register bit assignments
3.35. t_cke Register bit assignments
3.36. t_init_start Register bit assignments
3.37. mrr_data Register bit assignments
3.38. refresh_ctrl Register bit assignments
3.39. read_transfer_delay Register bit assignments
3.40. read_write_delay Register bit assignments
3.41. id_<n>_cfg registers bit assignments
3.42. chip_cfg<n> Registers bit assignments
3.43. user_status Register bit assignments
3.44. user_config0 Register bit assignments
3.45. user_config1 Register bit assignments
3.46. feature_ctrl Register bit assignments
3.47. int_cfg Register bit assignments
3.48. int_inputs Register bit assignments
3.49. int_outputs Register bit assignments
3.50. periph_id_[3:0] Register bit assignments
3.51. pcell_id Register bit assignments

List of Tables

2.1. Supported combinations of memory and AXI data widths
2.2. AXI slave interface attributes
2.3. Controller initialization example
2.4. memory_cfg and memory_cfg2 register example, for LPDDR devices
2.5. memory_cfg and memory_cfg2 Register example, for LPDDR2-S2 devices
2.6. LPDDR device initialization example
2.7. LPDDR2-S2 device initialization example
2.8. Valid system states for FSMs
2.9. Recommended power states
3.1. LPDDR2 DMC register summary
3.2. memc_status Register bit assignments
3.3. memc_cmd Register bit assignments
3.4. direct_cmd Register bit assignments
3.5. Memory command encoding
3.6. memory_cfg Register bit assignments
3.7. refresh_prd Register bit assignments
3.8. cas_latency Register bit assignments
3.9. write_latency Register bit assignments
3.10. t_mrd Register bit assignments
3.11. t_ras Register bit assignments
3.12. t_rc Register bit assignments
3.13. t_rcd Register bit assignments
3.14. t_rfc Register bit assignments
3.15. t_rp Register bit assignments
3.16. t_rrd Register bit assignments
3.17. t_wr Register bit assignments
3.18. t_wtr Register bit assignments
3.19. t_xp Register bit assignments
3.20. t_xsr Register bit assignments
3.21. t_esr Register bit assignments
3.22. memory_cfg2 Register bit assignments
3.23. Supported memory devices
3.24. memory_cfg3 Register bit assignments
3.25. t_faw Register bit assignments
3.26. t_phyupd_type Register bit assignments
3.27. t_rddata_en Register bit assignments
3.28. t_phywrlat Register bit assignments
3.29. t_rtp Register bit assignments
3.30. t_mrr Register bit assignments
3.31. t_cke Register bit assignments
3.32. t_init_start Register bit assignments
3.33. mrr_data Register bit assignments
3.34. refresh_ctrl Register bit assignments
3.35. read_transfer_delay Register bit assignments
3.36. read_write_delay Register bit assignments
3.37. id_<n>_cfg registers bit assignments
3.38. chip_cfg<n> registers bit assignments
3.39. user_status Register bit assignments
3.40. user_config0 Register bit assignments
3.41. user_config1 Register bit assignments
3.42. feature_ctrl registers bit assignments
3.43. int_cfg Register bit assignments
3.44. int_inputs Register bit assignments
3.45. int_outputs Register bit assignments
3.46. Conceptual peripheral ID Register bit assignments
3.47. periph_id_0 Register bit assignments
3.48. periph_id_1 Register bit assignments
3.49. periph_id_2 Register bit assignments
3.50. periph_id_3 Register bit assignments
3.51. pcell_id Register bit assignments
A.1. Clock and reset signals
A.2. QoS signal
A.3. Tie-off signals
A.4. User signals
A.5. Scan test signals
A.6. Write address channel signals
A.7. Write data channel signals
A.8. Write response channel signals
A.9. Read address channel signals
A.10. Read data channel signals
A.11. AXI low-power interface signals
A.12. APB interface signals
A.13. DFI pad interface signals
B.1. Issue A

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The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

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Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A17 September 2009Initial release for r0p0
Copyright © 2009 ARM. All rights reserved.ARM DDI 0436A
Non-Confidential