Cortex-A15 Technical Reference Manual: 4.3.59. L2 Prefetch Control Register

The L2PFR characteristics are:

Purpose

Provides control options for the L2 automatic hardware prefetcher.

Usage constraints

The L2PFR:

Is a read/write register.
Is Common to the Secure and Non-secure states.
Is only accessible from PL1 or higher, with access rights that depend on the mode:
- read/write in Secure PL1 modes
- read-only and write-ignored in Non-secure PL1 and PL2 modes.

Configurations

Available in all configurations.

Attributes

See the register summary in Table 4.14.

Figure 4.60 shows the L2PFR bit assignments.

Figure 4.60. L2PFR bit assignments

Table 4.75 shows the L2PFR bit assignments.

Table 4.75. L2 Prefetch Control Register bit assignments

Bits	Name	Function
[31:13]	-	Reserved, RAZ/WI.
[12]	Disable dynamic throttling of load/store prefetch requests	Disable dynamic throttling of load/store prefetch requests: 0 Enables dynamic throttling of load/store prefetch requests This is the reset value. 1 Disables dynamic throttling of load/store prefetch requests.
[11]	Enable prefetch requests from ReadUnique transactions	Enable prefetch requests from ReadUnique transactions: 0 Disables prefetch requests from being generated by ReadUnique transactions. 1 Enables prefetch requests to be generated by ReadUnique transactions. This is the reset value.
[10]	Disable table walk descriptor access prefetch	Disables table walk descriptor access prefetch: 0 Enables table walk descriptor access prefetch. This is the reset value. 1 Disables table walk descriptor access prefetch.
[9]	-	Reserved, RAZ/WI.
[8:7]	L2 instruction fetch prefetch distance	Indicates the L2 instruction fetch prefetch distance: `b00` 0 cache line. `b01` 1 cache line. `b10` 2 cache lines. `b11` 3 cache lines. This is the reset value.
[6]	-	Reserved, RAZ/WI.
[5:4]	L2 load/store data prefetch distance	L2 load/store data prefetch distance: `b00` 0 cache line. `b01` 2 cache lines. `b10` 4 cache lines. `b11` 8 cache lines. This is the reset value.
[3:0]	-	Reserved, RAZ/WI.

To access the L2PFR, read or write the CP15 register with:

MRC p15, 1, <Rt>, c15, c0, 3; Read L2 Prefetch Control Register

MCR p15, 1, <Rt>, c15, c0, 3; Write L2 Prefetch Control Register

Copyright © 2011 ARM. All rights reserved.	ARM DDI 0438C
Non-Confidential	ID102211
PDF version