Systems that are comprised of both the Cortex-A15 processor and other processors operating under a shared memory system must consider differences in the cache line length. The Cortex-A15 processor L1 caches contain 64-byte lines. Other processors, however, can feature L1 caches that contain 32-byte lines. System software often requires invalidation of a range of addresses that might be present in multiple processors. This is accomplished with a loop of invalidate cache by MVA CP15 operations that step through the address space in cache line-sized strides. For code to be portable across all ARMv7-A architecture-compliant devices, system software queries the CP15 Cache Type Register to obtain the stride size, see Cache Type Register for more information.

Systems that contain a combination of processors with 64-byte and 32-byte lines must handle data cache side operations within the interconnect, but it is not a requirement that the interconnect handles instruction side operations. The Cortex-A15 processor contains the IMINLN signal, that on reset, sets the value of the IminLine field within the Cache Type Register. You must set this signal 0 or 1, depending on the minimum instruction cache line size in the system. When IMINLN is set to 0, the minimum system-wide instruction cache line size is 32 bits. When IMINLN is set to 1, the minimum system-wide instruction cache line size is 64 bits. This signal is only sampled at reset.