Cortex-A15 Technical Reference ManualRevision: r2p0
Home > Signal Descriptions > PTM interface > ATB interface

A.11.1. ATB interface

Table A.28 shows the signals of the ATB interface. In this table, the value x represents processor 0, 1, 2, or 3 in your design.

Table A.28. ATB interface signals

SignalTypeDescription
AFREADYMxOutput

FIFO flush acknowledge:

0

FIFO flush not complete.

1

FIFO flush complete.

AFVALIDMxInput

FIFO flush request.

ATBYTESMx[1:0]Output

CoreSight ATB device data size:

b00

1 byte.

b01

2 byte.

b10

3 byte.

b11

4 byte.

ATDATAMx[31:0]Output

ATB data bus.

ATIDMx[6:0]Output

ATB trace source identification.

ATREADYMxInput

ATB device ready:

0

Not ready.

1

Ready.

ATVALIDMxOutput

ATB valid data:

0

No valid data.

1

Valid data.

ATCLKENInput

ATB clock enable.

SYNCREQxInput

Synchronization request. The input must be driven HIGH for one ATCLK cycle.


Copyright © 2011 ARM. All rights reserved.ARM DDI 0438C
Non-ConfidentialID102211
PDF file icon  PDF version
Home > Signal Descriptions > PTM interface > ATB interface