This signal initializes the processor logic, including the debug, Program Trace Macrocell (PTM), breakpoint, watchpoint logic, and performance monitors logic.

This signal resets the debug and PTM logic in the processor CLK domain, including the breakpoint and watchpoint logic. Performance monitors logic is not affected.

This signal initializes the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.