Cortex-A15 Technical Reference Manual: 14.2.4. Register descriptions

14.2.4. Register descriptions

This section describes the Cortex-A15 Advanced SIMD and VFP system registers. Table 14.3 provides cross references to individual registers.

Floating-Point System ID Register

The FPSID characteristics are:

Purpose: Provides top-level information about the floating-point implementation.
Usage constraints: Only accessible from PL1 or higher.
Configurations: Available if VFP is implemented.
Attributes: See the register summary in Table 14.3.

Figure 14.1 shows the FPSID bit assignments.

Figure 14.1. FPSID bit assignments

Table 14.4 shows the FPSID bit assignments.

Table 14.4. FPSID bit assignments

Bits	Name	Function
[31:24]	Implementer	Indicates the implementer: `0x41` ARM Limited.
[23]	SW	Software bit. This bit indicates that a system provides only software emulation of the VFP floating-point instructions: `0x0` The system includes hardware support for VFP floating-point operations.
[22:16]	Subarchitecture	Subarchitecture version number: `0x04` VFP architecture v4 with Common VFP subarchitecture v3. The VFP architecture version is indicated by the MVFR0 and MVFR1 registers.
[15:8]	Part number	Indicates the part number for the floating-point implementation: `0x30` VFP.
[7:4]	Variant	Indicates the variant number: `0xF` Cortex-A15.
[3:0]	Revision	Indicates the revision number for the floating-point implementation: `0x0` Revision.

Floating-Point Status and Control Register

The FPSCR characteristics are:

Purpose: Provides status information and control of unprivileged execution for the floating-point system.
Usage constraints: There are no usage constraints.
Configurations: Available if VFP is implemented.
Attributes: See the register summary in Table 14.3.

Figure 14.2 shows the FPSCR bit assignments.

Figure 14.2. FPSCR bit assignments

Table 14.5 shows the FPSCR bit assignments.

Table 14.5. FPSCR bit assignments

Bits	Field	Function
[31]	N	VFP Negative condition code flag. Set to 1 if a VFP comparison operation produces a less than result.
[30]	Z	VFP Zero condition code flag. Set to 1 if a VFP comparison operation produces an equal result.
[29]	C	VFP Carry condition code flag. Set to 1 if a VFP comparison operation produces an equal, greater than, or unordered result.
[28]	V	VFP Overflow condition code flag. Set to 1 if a VFP comparison operation produces an unordered result.
[27]	QC	Cumulative saturation bit. This bit is set to 1 to indicate that an Advanced SIMD integer operation has saturated since 0 was last written to this bit. If Advanced SIMD is not implemented, this bit is UNK/SBZP.
[26]	AHP	Alternative Half-Precision control bit: 0 IEEE half-precision format selected. 1 Alternative half-precision format selected.
[25]	DN	Default NaN mode control bit: 0 NaN operands propagate through to the output of a floating-point operation. 1 Any operation involving one or more NaNs returns the Default NaN. The value of this bit only controls VFP arithmetic. Advanced SIMD arithmetic always uses the Default NaN setting, regardless of the value of the DN bit.
[24]	FZ	Flush-to-zero mode control bit: 0 Flush-to-zero mode disabled. Behavior of the floating-point system is fully compliant with the IEEE 754 standard. 1 Flush-to-zero mode enable. The value of this bit only controls VFP arithmetic. Advanced SIMD arithmetic always uses the Flush-to-zero setting, regardless of the value of the FZ bit.
[23:22]	RMode	Rounding Mode control field: `b00` Round to Nearest (RN) mode. `b01` Round towards Plus Infinity (RP) mode. `b10` Round towards Minus Infinity (RM) mode. `b11` Round towards Zero (RZ) mode. The specified rounding mode is used by almost all VFP floating-point instructions. Advanced SIMD arithmetic always uses the Round to Nearest setting, regardless of the value of the RMode bits.
[21:20]	Stride	Use of non-zero value in this field for VFP short vector operation is deprecated in ARMv7. If this field is set to a non-zero value, the VFP data processing operations, except Vector Compare and Vector Convert instructions, generate an Undefined Instruction exception. See the ARM Architecture Reference Manual for more information.
[19]	-	UNK/SBZP.
[18:16]	Len	Use of non-zero value in this field for VFP short vector operation is deprecated in ARMv7. If this field is set to a non-zero value, the VFP data processing operations, except Vector Compare and Vector Convert instructions, generate an Undefined Instruction exception. See the ARM Architecture Reference Manual for more information.
[15]	-	RAZ/SBZP.
[14:13]	-	UNK/SBZP.
[12:8]	-	RAZ/SBZP.
[7]	IDC	Input Denormal cumulative exception bit.
[6:5]	-	UNK/SBZP.
[4]	IXC	Inexact cumulative exception bit.
[3]	UFC	Underflow cumulative exception bit.
[2]	OFC	Overflow cumulative exception bit.
[1]	DZC	Division by Zero cumulative exception bit.
[0]	IOC	Invalid Operation cumulative exception bit.

Media and VFP Feature Register 1

The MVFR1 characteristics are:

Purpose: Together with MVFR0, describes the features provided by the Advanced SIMD and VFP extensions.
Usage constraints: Only accessible from PL1 or higher.
Configurations: Available if VFP is implemented.
Attributes: See the register summary in Table 14.3.

Figure 14.3 shows the MVFR1 bit assignments.

Figure 14.3. MVFR1 bit assignments

Table 14.6 shows the MVFR1 bit assignments.

Table 14.6. MVFR1 bit assignments

Bits	Name	Function
[31:28]	A_SIMD FMAC	Indicates whether the Advanced SIMD or VFP supports fused multiply accumulate operations: `0x1` Supported.
[27:24]	VFP HPFP	Indicates whether the VFP supports half-precision floating-point conversion operations: `0x1` Supported.
[23:20]	A_SIMD HPFP	Indicates whether the Advanced SIMD extension supports half-precision floating-point conversion operations: `0x1` Supported. If Advanced SIMD is implemented, the reset value is `0x1`. If Advanced SIMD is not implemented, the reset value is `0x0`.
[19:16]	A_SIMD SPFP	Indicates whether the Advanced SIMD extension supports single-precision floating-point operations: `0x1` Supported. If Advanced SIMD is implemented, the reset value is `0x1`. If Advanced SIMD is not implemented, the reset value is `0x0`.
[15:12]	A_SIMD integer	Indicates whether the Advanced SIMD extension supports integer operations: `0x1` Supported. If Advanced SIMD is implemented, the reset value is `0x1`. If Advanced SIMD is not implemented, the reset value is `0x0`.
[11:8]	A_SIMD load/store	Indicates whether the Advanced SIMD extension supports load/store instructions: `0x1` Supported. If Advanced SIMD is implemented, the reset value is `0x1`. If Advanced SIMD is not implemented, the reset value is `0x0`.
[7:4]	D_NaN mode	Indicates whether the VFP hardware implementation supports only the Default NaN mode: `0x1` Hardware supports propagation of NaN values.
[3:0]	FtZ mode	Indicates whether the VFP hardware implementation supports only the Flush-to-Zero mode of operation: `0x1` Hardware supports full denormalized number arithmetic.

Media and VFP Feature Register 0

The MVFR0 characteristics are:

Purpose: Together with MVFR1, describes the features provided by the Advanced SIMD and VFP extensions.
Usage constraints: Only accessible from PL1 or higher.
Configurations: Available if VFP is implemented.
Attributes: See the register summary in Table 14.3.

Figure 14.4 shows the MVFR0 bit assignments.

Figure 14.4. MVFR0 bit assignments

Table 14.7 shows the MVFR0 bit assignments.

Table 14.7. MVFR0 bit assignments

Bits	Name	Function
[31:28]	VFP rounding modes	Indicates the rounding modes supported by the VFP floating-point hardware: `0x1` Supported.
[27:24]	Short vectors	Indicates the hardware support for VFP short vectors: `0x0` Not supported.
[23:20]	Square root	Indicates the hardware support for VFP square root operations: `0x1` Supported.
[19:16]	Divide	Indicates the hardware support for VFP divide operations: `0x1` Supported.
[15:12]	VFP exception trapping	Indicates whether the VFP hardware implementation supports exception trapping: `0x0` Not supported.
[11:8]	Double precision	Indicates the hardware support for VFP double-precision operations: `0x2` VFPv4 double-precision supported. See the ARM Architecture Reference Manual for more information.
[7:4]	Single precision	Indicates the hardware support for VFP single-precision operations: `0x2` VFPv4 single-precision supported. See the ARM Architecture Reference Manual for more information.
[3:0]	A_SIMD registers	Indicates support for the Advanced SIMD register bank: `0x2` 32 x 64-bit registers supported. See the ARM Architecture Reference Manual for more information.

Floating-Point Exception Register

The FPEXC characteristics are:

Purpose: Provides a global enable for the Advanced SIMD and VFP extensions, and indicates how the state of these extensions is recorded.
Usage constraints: Only accessible from PL1 or higher.
Configurations: Available if VFP is implemented.
Attributes: See the register summary in Table 14.3.

Figure 14.5 shows the FPEXC bit assignments.

Figure 14.5. FPEXC bit assignments

Table 14.8 shows the FPEXC Register bit assignments.

Table 14.8. FPEXC bit assignments

Bits	Name	Function
[31]	EX	Exception bit. The Cortex-A15 implementation does not generate asynchronous VFP exceptions, therefore this bit is RAZ/WI.
[30]	EN	Enable bit. A global enable for the Advanced SIMD and VFP extensions: 0 The Advanced SIMD and VFP extensions are disabled. 1 The Advanced SIMD and VFP extensions are enabled and operate normally. The EN bit is cleared at reset.
[29:26]	-	Reserved, RAZ/WI.
[25:0]	-	Reserved, UNK/SBZP.

Note

The Cortex-A15 implementation does not support deprecated VFP short vector feature. Attempts to execute VFP data-processing instructions, except VFP Compare and VFP Convert instructions, when the FPSCR.LEN field is non-zero result in an Undefined Instruction exception. You can use software to emulate the short vector feature, if required.

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