Table 12.1 shows
the options implemented in the Cortex-A15 PTM.
Table 12.1. Cortex-A15 PTM implementation options
| Resource | Implemented, or number of instances |
|---|
| Number of address comparators pairs | 4 |
| Context ID comparators | 1 |
| VM ID comparator | 1 |
| Embedded ICE watchpoint inputs | 0 |
| Counters | 2 |
| Sequencers | 1 |
| External inputs | 4 |
| External outputs | 2 |
| Extended external inputs, PMUEVENT | 88 |
| Extended external input selectors | 2 |
| Instrumentation resources | 0 |
| FIFOFULL supported | No |
| Software access to registers? | Yes |
| FIFO depth | 84 bytes |
| Trace output | Synchronous ATB interface |
| Timestamp size | 64 bits |
| Timestamp encoding | Natural binary |
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