| |||
| Home > System Control > Register summary > c0 registers | |||
Table 4.2 shows the 32-bit wide CP15 system control registers when CRn is c0.
Table 4.2. c0 register summary
| Op1 | CRm | Op2 | Name | Reset | Description |
|---|---|---|---|---|---|
| 0 | c0 | 0 | MIDR | 0x412FC0F0 | |
| 1 | CTR | 0x8444C004[a] | |||
| 2 | TCMTR | 0x00000000 | |||
| 3 | TLBTR | 0x00000000 | |||
| 4, 7 | MIDR | 0x411FC0F0 | Aliases of Main ID Register, Main ID Register | ||
| 5 | MPIDR | -[b] | |||
| 6 | REVIDR | 0x00000000 | Revision ID Register | ||
| c1 | 0 | ID_PFR0 | 0x00001131 | ||
| 1 | ID_PFR1 | 0x00011011 | |||
| 2 | ID_DFR0 | 0x02010555 | |||
| 3 | ID_AFR0 | 0x00000000 | Auxiliary Feature Register 0 | ||
| 4 | ID_MMFR0 | 0x10201105 | |||
| 5 | ID_MMFR1 | 0x20000000 | |||
| 6 | ID_MMFR2 | 0x01240000 | |||
| 7 | ID_MMFR3 | 0x02102211 | |||
| c2 | 0 | ID_ISAR0 | 0x02101110 | ||
| 1 | ID_ISAR1 | 0x13112111 | |||
| 2 | ID_ISAR2 | 0x21232041 | |||
| 3 | ID_ISAR3 | 0x11112131 | |||
| 4 | ID_ISAR4 | 0x10011142 | |||
| 5 | ID_ISAR5 | 0x00000000 | |||
| 1 | c0 | 0 | CCSIDR | UNK | |
| 1 | CLIDR | 0x0A200023 | |||
| 7 | AIDR | 0x00000000 | |||
| 2 | c0 | 0 | CSSELR | UNK | Cache Size Selection Register |
| 4 | c0 | 0 | VPIDR | -[c] | |
| 5 | VMPIDR | -[d] | Virtualization Multiprocessor ID Register | ||
[a] The reset value depends on the primary input, IMINLN. The value shown in Table 4.2 assumes IMINLN is set to 1. [b] The reset value depends on the primary input, CLUSTERID, and the number of configured processors in the MPCore device. [c] The reset value is the value of the Main ID Register. [d] The reset value is the value of the Multiprocessor Affinity Register. | |||||