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Table 4.23 shows the 32-bit wide miscellaneous operations.
Table 4.23. Miscellaneous system control operations
| Name | CRn | Op1 | CRm | Op2 | Reset | Description |
|---|---|---|---|---|---|---|
| NOP | c7 | 0 | c0 | 4 | UNK | System control No Operation (NOP), see the ARM Architecture Reference Manual |
| CP15ISB | c5 | 4 | UNK | Instruction Synchronization Barrier operation, see the ARM Architecture Reference Manual | ||
| CP15DSB | c10 | 4 | UNK | Data Synchronization Barrier operation, see the ARM Architecture Reference Manual | ||
| CP15DMB | 5 | UNK | Data Memory Barrier operation, see the ARM Architecture Reference Manual | |||
| NOP | c13 | 1 | UNK | System control No Operation (NOP), see the ARM Architecture Reference Manual | ||
| TPIDRURW | c13 | 0 | c0 | 2 | UNK | User Read/Write Thread ID Register, see the ARM Architecture Reference Manual |
| TPIDRURO | 3 | UNK | User Read-Only Thread ID Register, see the ARM Architecture Reference Manual | |||
| TPIDRPRW | 4 | UNK | PL1 only Thread ID Register, see the ARM Architecture Reference Manual | |||
| HTPIDR | 4 | c0 | 2 | UNK | Hyp Software Thread ID Register, see the ARM Architecture Reference Manual |
| Copyright © 2011 ARM. All rights reserved. | ARM DDI 0438C |
| Non-Confidential | ID102211 |
| PDF version | |
| Home > System Control > Register summary > Miscellaneous operations |